Abstract: Methods, systems, and devices for techniques for data programming are described for programming data to a memory system using a second programming mode associated with a higher error rate than a first programming mode. The second programming mode may include skipping one or more voltage calibration procedures included in the first programming mode, as well as performing one or more data verification procedures once a larger set of the data is programmed. The second programming mode may also include using a higher programming voltage pulse to program data and the programming pulse may last for a longer period of time than a programming pulse for the first programming mode. A memory system may receive data, determine to write the data to a memory device using the second programming mode, write the data using the second programming mode, and verify whether the data satisfies an error threshold.

Abstract: Systems and methods are disclosed comprising receiving L2P table information from a storage system over a communication interface, maintaining a host L2P table at a physical address using the received L2P table information, and providing a read command to the storage system for first data associated with a first LBA and a host L2P entry associated with the first data. The host L2P entry can include a physical address of the first LBA on the storage system according to the host L2P table and a physical address of a portion of the L2P table on the storage system associated with the first LBA. Control circuitry of the storage system can validate the physical address of the first LBA from the host L2P entry using the physical address of the portion of the host L2P table associated with the first LBA.

Abstract: Systems and methods are disclosed comprising receiving a request for a descriptor of a storage system, sending the descriptor to the host including an indication that a component of the storage device is in a restricted operation mode, wherein the host device utilizes the indication to determine a boot mode of the host device.

Abstract: A memory device embodiment may include an array of non-volatile memory cells including a protected memory region. The protected memory region may include a dedicated sub region established by a host. The memory device embodiment may also include a memory controller configured to wipe the protected memory region or execute other security functions by issuing an authenticated data write command to the dedicated sub region of the protected region. Issuing the authenticated data write command may include signing the command with a key shared with the host that established the sub region.

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

Abstract: Methods, systems, and devices that support efficient upload of firmware from memory are described. Multiple copies of a set of firmware may be stored across multiple planes of a memory device, such as with one respective copy within each of a set of planes. The copies may be staggered or otherwise offset in terms of page locations within the respective planes such that like-addressed pages within different planes store different subsets of the set of firmware. A controller may concurrently retrieve different subsets of the set of firmware, each of the different subsets included in a different copy, by concurrently retrieving the subsets stored at like-addressed pages within different memory planes. Upon loading the firmware code, the controller execute the firmware code to perform one or more further operations.

Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.

Abstract: Systems, apparatus, and methods are disclosed comprising receiving temperature information corresponding to a write temperature of at least one of multiple pages of non-volatile memory cells of a group of non-volatile memory cells, determining a statistical measure of temperature information for the group non-volatile memory cells using the received temperature information, and storing the determined statistical measure of temperature information for the group of non-volatile memory cells. The stored determined statistical measure of temperature information can be used to optimize or improve one or more storage system operations.

Abstract: Methods, systems, and devices for programming multi-level memory cells are described. After a first pass, an offset in the form of one or more offset pulses, may be applied to MLCs that are in a state of a higher level. The offset may be applied before or during a first part of a second pass. The offset may move the signals of the cells before the cells are finally programmed so as to avoid potential overlaps between the unprogrammed cells and cells that are programmed to the lower half of the final levels during the second pass. The offset cells may then be further moved to the other levels in the higher half of the final levels.

Abstract: Systems and methods are disclosed comprising receiving a request for a descriptor of a storage system, sending the descriptor to the host including an indication that a component of the storage device is in a restricted operation mode, wherein the host device utilizes the indication to determine a boot mode of the host device.

Abstract: Systems and methods are disclosed comprising receiving first-level L2P table information from a storage system over a communication interface, maintaining a host L2P table on using the received first-level L2P table information, and providing a read command to the storage system for first data associated with a first LBA and a host L2P entry associated with the first data. The host L2P entry can include a physical address of the first LBA on the storage system according to the host L2P table and a physical address of a portion of the L2P table on the storage system associated with the first LBA. Control circuitry of the storage system can validate the physical address of the first LBA from the host L2P entry using the physical address of the portion of the host L2P table associated with the first LBA and the second-level L2P table.

Abstract: Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information.

Abstract: Devices and techniques for command prioritization in a command queue of a memory device are described herein. A command can be received at the memory device. An expiration time for the command can be obtained and the command can be placed into the command queue. Entries in the command queue are ordered by expiration times of commands stored therein, such that earlier entries are closer to the head of the command queue. When the memory controller is able to perform a command, the memory controller selects the next command at the head of the command queue to perform.

Abstract: Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

Abstract: A memory device may include memory cells configured to establish multiple levels of charge distributions; and a memory controller configured to perform operations on the memory cells. The operations may include recording a bit count number for a highest level of charge distributions within a set of memory cells, recording a bit count number for a lowest level of charge distributions within the set of memory cells, counting bits for the highest level of charge distributions within the set of memory cells, counting bits in the lowest level of charge distributions within the set of memory cells, comparing the counted bits for the highest level to the recorded bit count number for the highest level, and comparing the counted bits for the lowest level to the recorded bit count number for the lowest level.

Abstract: Methods, systems, and devices for a memory access gate are described. A memory device may include a controller, memory dice, and a pad for receiving an externally provided control signal, such as a chip enable signal. The memory device may include a switching component for selecting the externally provided control signal or an internally generated control signal. The controller may provide the selected control signal to a memory die. The memory device may determine whether it is operating in a first mode or a second mode, and select the externally provided control signal or the internally generated control signal based on the determination. The first mode may be a diagnostic mode in some cases. The controller may include a secure register whose value may impact or control the switching. An authenticated host device may direct the controller to write the value to the secure register.

Abstract: Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.