Abstract: A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted.

Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Abstract: An on-chip receiver for flows of information conveyed to a target via optical signals with different wavelengths includes a plurality of photo-detector modules, each sensitive to a different wavelength, for converting a respective optical signal at input into an electrical signal, a plurality of de-serialization circuits acting on the electrical signals for converting into packet traffic the flows of information received via the photo-detector modules, and an arbitration node acting on the packet traffic to enable a single packet at a time to achieve the target.

Abstract: A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted.

Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Abstract: Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Abstract: An on-chip receiver for flows of information conveyed to a target via optical signals with different wavelengths includes a plurality of photo-detector modules, each sensitive to a different wavelength, for converting a respective optical signal at input into an electrical signal, a plurality of de-serialization circuits acting on the electrical signals for converting into packet traffic the flows of information received via the photo-detector modules, and an arbitration node acting on the packet traffic to enable a single packet at a time to achieve the target.

Abstract: Data transport is provided in a communication network such as a Network-on-Chip arrangement via full-duplex mesochronous links between routers. Request signals and response signals are exchanged between these routers acting alternatively as an initiator and a target operating in respective clock domains at opposite ends of respective full-duplex mesochronous links. The request initiator flow control signals are monitored at the target end of the link while the response target flow control signals are monitored at the initiator end of the link. The monitoring action involves ascertaining if a request has been granted at the initiator end of the link and if a response has been granted at the target end of said link thus correspondingly managing the data flow over the link.

Abstract: Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Abstract: Data transport is provided in a communication network such as a Network-on-Chip arrangement via full-duplex mesochronous links between routers. Request signals and response signals are exchanged between these routers acting alternatively as an initiator and a target operating in respective clock domains at opposite ends of respective full-duplex mesochronous links. The request initiator flow control signals are monitored at the target end of the link while the response target flow control signals are monitored at the initiator end of the link. The monitoring action involves ascertaining if a request has been granted at the initiator end of the link and if a response has been granted at the target end of said link thus correspondingly managing the data flow over the link.