Patents by Inventor Glen A. Wiedemeier
Glen A. Wiedemeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804828Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.Type: GrantFiled: February 22, 2022Date of Patent: October 31, 2023Assignee: International Business Machines CorporationInventors: Jieming Qi, Daniel Mark Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie Ellen Cox, Timothy O. Dickson
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Patent number: 11775002Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.Type: GrantFiled: July 27, 2021Date of Patent: October 3, 2023Assignee: International Business Machines CorporationInventors: Matthew James Paschal, Daniel M. Dreps, Glen A. Wiedemeier, Bruce George Rudolph, James Strom
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Publication number: 20230268908Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Inventors: Jieming Qi, Daniel Mark Dreps, Glen A. Wiedemeier, Eric John Lukes, Carrie Ellen Cox, Timothy O. Dickson
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Patent number: 11714449Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.Type: GrantFiled: September 27, 2021Date of Patent: August 1, 2023Assignee: International Business Machines CorporationInventors: Ze Zhang, Dereje Yilma, Chad Andrew Marquart, Glen A. Wiedemeier
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Publication number: 20230214573Abstract: Embodiments include thermally coupled aware device placement in the schematic design stage of the development of an integrated circuit. Aspects of the invention include obtaining a schematic design of a macro, the schematic design including a plurality of devices disposed within the macro. Aspects also include determining an initial temperature for each of the plurality of devices, where the initial temperature due to self-heating. Aspects further include determining, iteratively for each of the plurality of devices, an uplift temperature, where the uplift temperature for a first device of the plurality of devices is determined based on the initial temperature of each of the other plurality of devices and a distance between the first device and each of the other plurality of devices as encoded in the schematic design. Aspects also include modifying the schematic design of the macro based on a determination that the uplift temperature of at least one of the plurality of devices is above a threshold value.Type: ApplicationFiled: January 4, 2022Publication date: July 6, 2023Inventors: Akil Khamisi Sutton, Peter A Smith, Glen A. Wiedemeier, William Edward Ansley, John Greg Massey
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Patent number: 11662381Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.Type: GrantFiled: August 18, 2021Date of Patent: May 30, 2023Assignee: International Business Machines CorporationInventors: Nathan Ross Blanchard, Venkat Harish Nammi, Dereje Yilma, Chad Andrew Marquart, Glen A. Wiedemeier, Jeffrey Kwabena Okyere, Erik English, Christopher Steffen, Vikram B Raj, Michael Wayne Harper
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Patent number: 11632103Abstract: A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.Type: GrantFiled: September 20, 2021Date of Patent: April 18, 2023Assignee: International Business Machines CorporationInventors: Chad Andrew Marquart, Glen A. Wiedemeier, Daniel M. Dreps
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Publication number: 20230099810Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Inventors: Ze Zhang, Dereje Yilma, Chad Andrew Marquart, Glen A. Wiedemeier
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Publication number: 20230088871Abstract: A high-speed voltage clamping circuit includes p-type field effect transistor (PFET) biasing circuit, an n-type field effect transistor (NFET) biasing circuit, and a field effect transistor (FET) clamp circuit. The PFET biasing circuit is configured to generate a PFET biasing voltage. The NFET biasing circuit is configured to generate a NFET biasing voltage. The FET clamp circuit is in signal communication with the PFET biasing circuit and the NFET biasing circuit. The PFET biasing circuit controls operation of the clamping circuit in response to a voltage overshoot event and the NFET biasing circuit controls operation of the clamping circuit in response to a voltage undershoot event.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Chad Andrew Marquart, Glen A. Wiedemeier, Daniel M. Dreps
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Patent number: 11606082Abstract: A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.Type: GrantFiled: May 20, 2021Date of Patent: March 14, 2023Assignee: International Business Machines CorporationInventors: Yang You, Chad Andrew Marquart, Glen A. Wiedemeier, Tyler Bohlke, Daniel M. Dreps
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Publication number: 20230055935Abstract: Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.Type: ApplicationFiled: August 18, 2021Publication date: February 23, 2023Inventors: Nathan Ross Blanchard, VENKAT HARISH NAMMI, DEREJE YILMA, Chad Andrew Marquart, Glen A. Wiedemeier, JEFFREY KWABENA OKYERE, Erik English, Christopher Steffen, Vikram B. Raj, Michael Wayne Harper
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Publication number: 20230035405Abstract: A first oscillator signal and a second oscillator signal are transmitted to a processing unit. The first oscillator signal has a finite frequency or phase offset relative to the second oscillator signal. A first clock signal that is derived from the first oscillator signal is selected as a primary clock to clock the processing unit. A second clock signal derived from the second oscillator signal is aligned to the first clock signal. If a fault is detected on the first clock signal, the second clock signal is selected as the primary clock to clock the processing unit. Upon being selected as the primary clock, the phase of the second is stretched by one fixed phase for one clock cycle.Type: ApplicationFiled: July 27, 2021Publication date: February 2, 2023Inventors: Matthew James Paschal, Daniel M. Dreps, Glen A. Wiedemeier, Bruce George Rudolph, James Strom
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Patent number: 11558045Abstract: A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.Type: GrantFiled: June 29, 2021Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Yang You, Venkat Harish Nammi, Pier Andrea Francese, Chad Andrew Marquart, Glen A. Wiedemeier, Daniel M. Dreps
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Publication number: 20220416774Abstract: A method includes connecting inputs of a first plurality of interpolation branches to a first clock signal, connecting inputs of a second plurality of interpolation branches to a second clock signal, and connecting inputs of a third plurality of interpolation branches to a third clock signal. The method also includes combining outputs of the first plurality of interpolation branches, the second plurality of interpolation branches, and the third plurality of interpolation branches to produce an output clock signal and adjusting a phase of the output clock signal by connecting an input of an interpolation branch of the third plurality of interpolation branches to the second clock signal.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Inventors: Yang YOU, Venkat Harish NAMMI, Pier Andrea FRANCESE, Chad Andrew MARQUART, Glen A. WIEDEMEIER, Daniel M. DREPS
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Patent number: 11528102Abstract: Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.Type: GrantFiled: August 18, 2021Date of Patent: December 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dereje Yilma, Nathan Ross Blanchard, Erik English, Chad Andrew Marquart, Glen A. Wiedemeier, Jeffrey Kwabena Okyere, James Crugnale, Christopher Steffen, Vikram B Raj, Michael Wayne Harper, Venkat Harish Nammi
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Publication number: 20220376677Abstract: A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.Type: ApplicationFiled: May 20, 2021Publication date: November 24, 2022Inventors: Yang YOU, Chad Andrew MARQUART, Glen A. WIEDEMEIER, Tyler BOHLKE, Daniel M. DREPS
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Patent number: 10958248Abstract: A method and apparatus are described to implement a bandpass filter in a current mode logic (CML) stage of a clock tree in an electronic system. The bandpass filter has a bandpass filter transfer function to attenuate frequencies lower than and higher than a carrier frequency. The bandpass filter uses adjustable active inductors and capacitive source degeneration. Adjustable resistors may be controlled to move a peak frequency of the bandpass filter transfer function to a higher or lower frequency. The adjustable active inductors and capacitive degeneration may consist of field effect transistors.Type: GrantFiled: May 27, 2020Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yang You, Glen A. Wiedemeier, Chad Andrew Marquart, Jeffrey Kwabena Okyere, Daniel M. Dreps, Sudipto Chakraborty
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Patent number: 10826810Abstract: A method and apparatus in a receiver to determine if a high speed communication link is in an idle mode or in an active mode. Signals during the idle mode are of lower amplitude and lower frequency compared to amplitude and frequency in the active mode. A signal detector in the receiver determines if the high speed communication link has transitioned from idle mode to active mode and, if so, wakes up high power circuitry in the receiver to receive data.Type: GrantFiled: September 30, 2019Date of Patent: November 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yang You, Pier Andrea Francese, Glen Wiedemeier, Daniel M. Dreps, Chad Andrew Marquart
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Patent number: 9912324Abstract: Embodiments described herein include a quadrature phase corrector (QPC) which includes multiple differential amplifies for correcting the phase of one or more clock signals. In one embodiment, the differential amplifiers are arranged in an input stage, cross-coupled stage, and ring stage. The input stage receives and buffers the input clock signal (or signals). The cross-coupled stage includes one or more latches that force one clock signal high and another low which causes the QPC to oscillate. The ring stage outputs four clock signals with adjusted phases relative to the input clock signals. In one example, the ring stage outputs a quadrature clock signal that includes four clock signals phase shifted by 90 degrees.Type: GrantFiled: September 1, 2015Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul W. Coteus, Daniel M. Dreps, Kyu-hyoun Kim, Glen A. Wiedemeier
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Patent number: 9733305Abstract: Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.Type: GrantFiled: August 24, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Glen A. Wiedemeier, Si T. Win