Patents by Inventor Glen Howard Handlogten
Glen Howard Handlogten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6987760Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.Type: GrantFiled: April 19, 2001Date of Patent: January 17, 2006Assignee: International Business Machines CorporationInventors: Jean Louis Calvignac, William John Goetzinger, Glen Howard Handlogten, Marco C. Heddes, Joseph Franklin Logan, James Francis Mikos, David Alan Norgaard, Fabrice Jean Verplanken
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Patent number: 6982986Abstract: A QoS scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling with detecting and anticipating the end of a chain of flows. A first indicator is provided for indicating a number of flows being chained to a physical entry. A second indicator is provided for indicating when the first indicator has saturated. The second indicator is set active for a flow whose chaining causes the first indicator to saturate. During de-chaining of the flows from the physical entry, the second indicator is used to determine when the first indicator becomes accurate to begin decrementing the first indicator. The first indicator is decremented for detecting the end of the chain of flows. Responsive to the first indicator being not saturated, the first indicator is used for anticipating the end of a chain of flows. The first indicator and the second indicator include a predefined number of bits or n-bits.Type: GrantFiled: November 1, 2001Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Patent number: 6973036Abstract: A scheduler and scheduling method implement peak service distance using a next peak service time violated (NPTV) indication. A flow scheduled on a best effort or weighted fair queue (WFQ) is identified for servicing and a frame is dispatching from the identified flow. A next PSD time (NPT) being violated is checked for the flow. Responsive to identifying the next PSD time (NPT) being violated for the identified flow, a NPTV indicator is set. Alternatively, responsive to identifying the next PSD time (NPT) not being violated for the identified flow, the NPTV indicator is reset. A next PSD time (NPT) value is calculated for the flow. Checking for more frames to be dispatched from the flow is performed. Responsive to identifying no more frames to be dispatched from the flow, the NPTV indicator is utilized to identify a calendar for attaching the flow upon a new frame arrival for the flow.Type: GrantFiled: November 1, 2001Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20040114517Abstract: A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.Type: ApplicationFiled: December 12, 2002Publication date: June 17, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lyle Edwin Grosbach, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20040017781Abstract: In a scheduler circuit for a network processor, bandwidth assigned to a virtual path is allocated among virtual channels associated with the virtual path. The allocation of bandwidth among the virtual channels is varied dynamically as virtual channels become active or inactive.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Merwin Herscher Alferness, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Patent number: 6684232Abstract: During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.Type: GrantFiled: October 26, 2000Date of Patent: January 27, 2004Assignee: International Business Machines CorporationInventors: Glen Howard Handlogten, James Edward Phillips, Lawrence Joseph Powell, Martin Stanley Schmookler
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Publication number: 20030179765Abstract: In a first aspect, a network processor includes a scheduler in which a scheduling queue is maintained. A last frame is dispatched from a flow queue maintained in the network processor, thereby emptying the flow queue. Data indicative of the size of the dispatched last frame is stored in association with the scheduler. A new frame corresponding to the emptied flow queue is received, and the flow corresponding to the emptied flow queue is attached to the scheduling queue. The flow is attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is determined based at least in part on the stored data indicative of the size of the dispatched last frame.Type: ApplicationFiled: March 20, 2002Publication date: September 25, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030179706Abstract: In a first aspect, a network processor services a plurality of flows including a first flow and a discard flow. The first flow includes a first flow queue and the discard flow includes a discard queue that lists frames to be discarded. An indication is made that the first flow is to be disabled. In response to the indication, all frames included in the first flow queue are transferred to the discard queue. Because the first flow queue is now empty, reconfiguration of the first flow may proceed immediately.Type: ApplicationFiled: March 20, 2002Publication date: September 25, 2003Applicant: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081611Abstract: A scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling of a plurality of flows with aging time stamps. Subsets of time stamp data stored in a time stamp aging memory array are sequentially accessed. Each time stamp data subset contains time stamp data for a subplurality of flows. Guaranteed aging processing steps are performed for each flow utilizing the time stamp data subsets to identify and mark invalid calendar next time values. When a new frame arrival for an empty flow is identified, flow queue control block (FQCB) time stamp data and the flow time stamp data in the time stamp aging memory array are accessed. Based on the calendar to which the new frame is directed or the target calendar for the new frame, the target calendar next time valid bit of the time stamp aging memory array data is checked.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Inventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081542Abstract: A scheduler for a network processor includes one or more scheduling queues. Each scheduling queue defines a respective sequence in which flows are to be serviced. A respective empty indicator is associated with each scheduling queue to indicate whether the respective scheduling queue is empty. By referring to the empty indicators, it is possible to avoid wasting operating cycles of the scheduler on searching scheduling queues that are empty.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard, Daniel James Sucher
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Publication number: 20030081544Abstract: A QoS scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling with a cached status array. A plurality of calendars are provided for scheduling the flows. An active flow indicator is stored for each calendar entry in a calendar status array (CSA). A cache copy subset of the active flow indicators from the calendar status array (CSA) is stored in a cache. The calendar status array (CSA) is updated based upon a predefined calendar range and resolution. The cache copy subset of the active flow indicators from the calendar status array (CSA) is used to determine a given calendar for servicing.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081549Abstract: A data communication apparatus includes a plurality of output ports and a scheduler for assigning priorities for outbound data frames. The scheduler includes one or more scheduling queues. Each scheduling queue indicates an order in which data flows are to be serviced. At least one scheduling queue has a respective plurality of output ports assigned to the scheduling queue. That is, the scheduling queue is shared by two or more output ports.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081612Abstract: A QoS scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling with detecting and anticipating the end of a chain of flows. A first indicator is provided for indicating a number of flows being chained to a physical entry. A second indicator is provided for indicating when the first indicator has saturated. The second indicator is set active for a flow whose chaining causes the first indicator to saturate. During de-chaining of the flows from the physical entry, the second indicator is used to determine when the first indicator becomes accurate to begin decrementing the first indicator. The first indicator is decremented for detecting the end of the chain of flows. Responsive to the first indicator being not saturated, the first indicator is used for anticipating the end of a chain of flows. The first indicator and the second indicator include a predefined number of bits or n-bits.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Inventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081543Abstract: A scheduler and scheduling method implement peak service distance using a next peak service time violated (NPTV) indication. A flow scheduled on a best effort or weighted fair queue (WFQ) is identified for servicing and a frame is dispatching from the identified flow. A next PSD time (NPT) being violated is checked for the flow. Responsive to identifying the next PSD time (NPT) being violated for the identified flow, a NPTV indicator is set. Alternatively, responsive to identifying the next PSD time (NPT) not being violated for the identified flow, the NPTV indicator is reset. A next PSD time (NPT) value is calculated for the flow. Checking for more frames to be dispatched from the flow is performed. Responsive to identifying no more frames to be dispatched from the flow, the NPTV indicator is utilized to identify a calendar for attaching the flow upon a new frame arrival for the flow.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081552Abstract: A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied. The scheduling queue has a range R. Flows are attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is calculated for each flow according to the formula D=((WF×FS)/SF), where WF is a weighting factor applicable to a respective flow; FS is a frame size attributable to the respective flow; and SF is a scaling factor. The scaling factor SF is adjusted depending on a comparison of the distance D to the range R.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20030081545Abstract: A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied to define a sequence in which flows are to be serviced. The scheduling queue includes at least a first subqueue and a second subqueue. The first subqueue has a first range and a first resolution, and the second subqueue has an extended range that is greater than the first range and a lower resolution that is less than the first resolution. Flows that are to be enqueued within the range of highest precision to the current pointer of the scheduling queue are attached to the first subqueue. Flows that are to be enqueued outside the range of highest precision from the current pointer of the scheduling queue are attached to the second subqueue. Numerous other aspects are provided.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: International Business Machines CorporationInventors: William John Goetzinger, Glen Howard Handlogten, James Francis Mikos, David Alan Norgaard
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Publication number: 20020122386Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.Type: ApplicationFiled: April 19, 2001Publication date: September 5, 2002Applicant: International Business Machines CorporationInventors: Jean Louis Calvignac, William John Goetzinger, Glen Howard Handlogten, Marco C. Heddes, Joseph Franklin Logan, James Francis Mikos, David Alan Norgaard, Fabrice Jean Verplanken
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Patent number: 5943249Abstract: A method of processing a floating-point instruction (including a multiply-add instruction) in a floating-point processor. Prior-art techniques require prenormalization of intermediate results generated by the floating-point processor, but normalization can sometimes result in an underflow condition, which requires denormalizing the intermediate result. The present invention provides a method of determining an amount to shift the mantissa of the intermediate result to obtain a final result while avoiding ever producing an exponent that is out of range. The invention also allows denormalized numbers to be stored in the floating-point registers in a denormalized form. The method of determining the shift amount first requires a determination of whether both, or only one, of the product and adder operands are denormalized. If both are denormalized, then the shift amount is equal to the addend alignment amount.Type: GrantFiled: April 25, 1997Date of Patent: August 24, 1999Assignee: International Business Machines CorporationInventor: Glen Howard Handlogten