Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

Abstract: An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.

Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and III-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

Abstract: An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

Abstract: Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium, zinc, carbon, beryllium, and the like, may be introduced in the formation of the sub-structure, wherein the dopant may act as a p/n junction at the active channel to source and drain interfaces and decrease the off-state leakage path. In another embodiment, the material used for the formation of the doped sub-structure may be substantially the same as the material, without the dopant, used for the formation of the active channel, such that no heterojunction will be formed which could result in crystalline imperfections.

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.

Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

Abstract: Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.