Patents by Inventor Glenn D. Gilda
Glenn D. Gilda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10684968Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.Type: GrantFiled: June 15, 2017Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David D. Cadigan, Thomas J. Dewkett, Glenn D. Gilda, Patrick J. Meaney, Craig R. Walters
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Patent number: 10558519Abstract: Embodiments include techniques used for a power-reduced redundant array of independent memory RAIM system. The technique includes blocking commands to one or more memory modules of the RAIM system and reading data from one or more unblocked memory modules. The technique also includes applying a power channel mark for one or more blocked memory modules, the power channel mark indicating the one or more blocked memory modules to a decoder for error correction.Type: GrantFiled: January 17, 2017Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney
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Patent number: 10296417Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.Type: GrantFiled: July 24, 2018Date of Patent: May 21, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney
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Patent number: 10254961Abstract: A computer-implemented method for managing a memory control unit includes receiving a command at the memory control unit. The command includes a command type that either requires or does not require buffering resources. The method further includes determining, via the memory control unit, a number of available memory tags from a first set of memory tags that are associated with the buffering resources. The method includes determining, via the memory control unit, a number of available memory tags from a second set of memory tags that are not associated with the buffering resources. The method also includes dynamically adjusting, via the memory control unit, assignment of memory tags for use in the second set of memory tags based on the command type, the number of available memory tags from the first set of memory tags, and the number of available memory tags from the second set of memory tags.Type: GrantFiled: February 21, 2017Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Mark R. Hodges
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Publication number: 20180367166Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.Type: ApplicationFiled: December 4, 2017Publication date: December 20, 2018Inventors: Glenn D. Gilda, Patrick J. Meaney, Arthur O'Neill, Barry M. Trager
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Publication number: 20180365177Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.Type: ApplicationFiled: June 15, 2017Publication date: December 20, 2018Inventors: David D. Cadigan, Thomas J. Dewkett, Glenn D. Gilda, Patrick J. Meaney, Craig R. Walters
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Publication number: 20180329777Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: Glenn D. Gilda, Patrick J. Meaney
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Publication number: 20180239534Abstract: A computer-implemented method for managing a memory control unit includes receiving a command at the memory control unit. The command includes a command type that either requires or does not require buffering resources. The method further includes determining, via the memory control unit, a number of available memory tags from a first set of memory tags that are associated with the buffering resources. The method includes determining, via the memory control unit, a number of available memory tags from a second set of memory tags that are not associated with the buffering resources. The method also includes dynamically adjusting, via the memory control unit, assignment of memory tags for use in the second set of memory tags based on the command type, the number of available memory tags from the first set of memory tags, and the number of available memory tags from the second set of memory tags.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Inventors: Glenn D. Gilda, Mark R. Hodges
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Patent number: 10055287Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.Type: GrantFiled: November 13, 2017Date of Patent: August 21, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney
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Publication number: 20180203627Abstract: Embodiments include techniques used for a power-reduced redundant array of independent memory RAIM system. The technique includes blocking commands to one or more memory modules of the RAIM system and reading data from one or more unblocked memory modules. The technique also includes applying a power channel mark for one or more blocked memory modules, the power channel mark indicating the one or more blocked memory modules to a decoder for error correction.Type: ApplicationFiled: January 17, 2017Publication date: July 19, 2018Inventors: GLENN D. GILDA, PATRICK J. MEANEY
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Patent number: 9946595Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.Type: GrantFiled: September 30, 2015Date of Patent: April 17, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney
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Publication number: 20180060167Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.Type: ApplicationFiled: November 13, 2017Publication date: March 1, 2018Inventors: Glenn D. Gilda, Patrick J. Meaney
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Publication number: 20170091023Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Glenn D. Gilda, Patrick J. Meaney
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Patent number: 9594646Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a computer implemented method that includes receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system. A memory control unit in communication with the channels performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.Type: GrantFiled: August 31, 2016Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova, John S. Dodson
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Patent number: 9594647Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.Type: GrantFiled: September 12, 2016Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick J. Meaney, Glenn D. Gilda, Eric E. Retter, John S. Dodson, Gary A. Van Huben, Brad W. Michael, Stephen J. Powell
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Patent number: 9563548Abstract: Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.Type: GrantFiled: August 11, 2015Date of Patent: February 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence D. Curley, Glenn D. Gilda, Patrick J. Meaney
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Patent number: 9535778Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.Type: GrantFiled: March 15, 2013Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova, John S. Dodson
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Publication number: 20160371159Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.Type: ApplicationFiled: September 12, 2016Publication date: December 22, 2016Inventors: Patrick J. Meaney, Glenn D. Gilda, Eric E. Retter, John S. Dodson, Gary A. Van Huben, Brad W. Michael, Stephen J. Powell
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Publication number: 20160364303Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a computer implemented method that includes receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system. A memory control unit in communication with the channels performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.Type: ApplicationFiled: August 31, 2016Publication date: December 15, 2016Inventors: Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova, John S. Dodson
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Patent number: 9495231Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.Type: GrantFiled: March 17, 2016Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Glenn D. Gilda, Patrick J. Meaney, Vesselina K. Papazova, John S. Dodson