Abstract: Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract: To prevent data performance impacts when dealing with target devices that can only transfer data for a limited number of bytes before disconnecting, the invention implements a short term data cache on the bridge. Using this feature, the bridge will cache additional data beyond a predetermined quantity of data following a disconnect with the requesting device. As such, the bridge may continue to prefetch additional data up to an amount specified by a prefetch read byte count and return the additional data should the requesting device request additional data resuming at the point of disconnect. However, the bridge will discard the additional data when at least one of the following occurs: a) the requesting device disconnects data transfer, and b) a further READ request that resumes at the point of disconnect is not received within a predetermined time.

Abstract: To prevent data performance impacts when dealing with target devices that can only transfer data for a limited number of bytes before disconnecting, the invention implements a short term data cache on the bridge. Using this feature, the bridge will cache additional data beyond a predetermined quantity of data following a disconnect with the requesting device. As such, the bridge may continue to prefetch additional data up to an amount specified by a prefetch read byte count and return the additional data should the requesting device request additional data resuming at the point of disconnect. However, the bridge will discard the additional data when at least one of the following occurs: a) the requesting device disconnects data transfer, and b) a further READ request that resumes at the point of disconnect is not received within a predetermined time.

Abstract: A computer system comprises a data processor, a main memory, a cache memory and an inpage buffer. The cache memory is coupled to the main memory to receive data therefrom and is coupled to the processor to transfer data thereto. The inpage buffer is coupled to the main memory to receive data therefrom, coupled to the cache memory to transfer data thereto, and coupled to the processor to transfer data thereto. Part of a line of data is originally transferred to the cache memory bypassing the inpage buffer to give the processor immediate access to the data which it needs. The remainder of the line of data is subsequently transferred to the inpage buffer, and then the processor is given access to the contents of the inpage buffer. The processor accesses the data in the cache memory with one set of clocks while the remainder of the line of data is transferred to the inpage buffer with another set of clocks. The two sets of clocks optimize the operation of tile processor and the main memory.

Abstract: A portable thermocouple template is built to have one or more separate thermocouple beads fixedly attached at predetermined locations on a thin insulator sheet, with appropriate tape or the like for holding each thermocouple and its pair of connector wires in position on the sheet. The template is mountable between interconnected electronic components, such as on the pin side of a multichip module, in order to monitor the temperature of the adjacent components under actual operating conditions. After the test is completed and the temperature data is recorded and/or displayed on a data logger, the template and related assembly wires are removed and stored until such time as the template is needed for mounting again in order for additional thermal tests to be conducted.