Abstract: A mechanical release for an electric parking brake has a first cable engaging a housing. A second cable is connected to a lever that is pivotally supported on the housing by a pivot pin. A locking member engages the lever and prevents rotation of the lever when tension is applied to the cables. When the locking member is released, the lever is free to rotate, reducing tension in the cables and freeing the parking brake system.

Abstract: A mechanical release for an electric parking brake has a first cable engaging a housing. A second cable is connected to a lever that is pivotally supported on the housing by a pivot pin. A locking member engages the lever and prevents rotation of the lever when tension is applied to the cables. When the locking member is released, the lever is free to rotate, reducing tension in the cables and freeing the parking brake system.

Abstract: A set of processors and instruction set for a pipelined multiprocessing architecture with separate code and data streams is disclosed. The overall architecture considered interlocks instruction execution with the destination transfer of results and includes automated input and output of array data. The data is dispensed from a central memory that is associated with the control unit and all results and inputs are automatically returned to this central memory over a second bus. Once the processors receive their data they operate independently and several instructions may be in the process of being executed at the same time with destination validity checking being used to coordinate the activity. The central memory may contain partitions, called circular partitions, or first-in/first-out buffers which make it possible for it to automatically prefetch or output array data. The instructions include overlapping address and operand length bits.

Abstract: An intermediate data buffer for prefetching data from main memory and supplying it to a processing element and taking results from the processing element and outputting them to main memory is disclosed. The apparatus, referred to as a windowed programmable data buffer (WPDB), is a programmable, one-port or two-port circular data buffer that can simultaneously input data from or output results to main memory and output data to or input results from a processing element. The transfer of data between the WPDB and main memory is separated from the transfer of data between the WPDB and the processing element by means of a window. The transfers with the main memory use the locations outside the window and the transfers with the processing element use the locations inside of the window. The window may be programmed to increment forward around the circular buffer or remain stationary. The WPDB can operate in two modes. One mode uses offsets sent by the processing element to access data within the window.

Abstract: An intermediate code memory for taking instructions from main memory and supplying them inline to a processing element is disclosed. Inputting instructions into the intermediate code memory from main memory is done using a DMA channel and may be done simultaneously with outputting instructions to the processing element. Outputting can be done from any location that is outside a dynamic window, whose position and size depend on the area in the code memory to which the code is currently being input. In addition, the code memory contains a LIFO stack and executes all subprogram call and return instructions so that the instructions presented to the processing element are inline. Normally, the instructions are output sequentially from the code memory, however, subprogram calls and returns, certain unconditional branch instructions executed by the intermediate code memory, and addresses passed from the processing element may change the instruction sequence.

Abstract: Method and apparatus for prefetching and buffering instructions between a code store and a processing element's decode logic. The apparatus is a code buffer that consists of a code RAM and its supporting logic that implements rules for bringing instructions into the code RAM from the code store and outputting them to the decode logic. These rules determine when writing to the code RAM is blocked and reading from the code RAM is blocked by using the write and read addresses and loop information stored in the supporting logic. The rules guarantee that the instructions to be executed are not overwritten, instructions being executed have, in fact, been brought into the code RAM, and loops are kept in the code RAM until they have been exited. The code buffer handles two types of branch instructions, inside branches to instructions that are within the code RAM and outside branches to instructions in the code store.

Abstract: Irrigation controller apparatus for respectively controlling moisture content in a plurality of irrigation zones including an independently actuated moisture detection apparatus in each zone which stops and starts irrigation in that zone depending on moisture detected by the respective apparatus.