Abstract: An arithmetic processing device has a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory and a first cache unit, and a second arithmetic processing unit including a second instruction controller and a second cache unit. The first arithmetic processing unit transmits an invalidation request to the second arithmetic processing unit when a write request to the memory is issued within a first transaction, and in response to the invalidation request, the second cache unit determines whether a second transaction is to be aborted based on information in the invalidation request when the second transaction conflicts with the first transaction for a cache block corresponding to a destination of the write request, and sends a determination result to the first arithmetic processing unit.

Abstract: A central processing unit, connected to a main memory among a plurality of central processing units each including a cache memory, includes a control unit. The control unit executes a process including: classifying the plurality of central processing units into a smaller number than a total number of the plurality of central processing units, and writing to the main memory presence information indicating whether or not the same data as data stored in the main memory is held in a cache memory included in any of the central processing units that belong to a corresponding central processing unit group, for each central processing unit group of a plurality of central processing unit groups obtained by the classifying.

Abstract: An arithmetic processing device has a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory and a first cache unit, and a second arithmetic processing unit including a second instruction controller and a second cache unit. The first arithmetic processing unit transmits an invalidation request to the second arithmetic processing unit when a write request to the memory is issued within a first transaction, and in response to the invalidation request, the second cache unit determines whether a second transaction is to be aborted based on information in the invalidation request when the second transaction conflicts with the first transaction for a cache block corresponding to a destination of the write request, and sends a determination result to the first arithmetic processing unit.

Abstract: An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt.

Abstract: An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended.

Abstract: A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor.

Abstract: An information processing apparatus including a plurality of mutually connected system boards, wherein each of the system boards includes: a plurality of processors; and a plurality of memories each of which stores data and directory information corresponding to the data, and corresponds to any one of the processors, and wherein each of the plurality of processors, upon receiving a read request for data stored in a memory corresponding to the own processor from another processor, performs an exclusive logical sum operation on identification information included in the read request and identifying the another processor and a check bit included in the directory information and identifying a processor which holds target data of the read request, increments a count value included in the directory information and indicating the number of processors which hold the target data, and sets presence information included in the directory information and indicating a system board which includes the another processor.

Abstract: A system controller includes an output unit which transfers an access request from an access source coupled to the system controller to an other system controller; a local snoop control unit that determines whether a destination of the access request from the access source is a local memory unit coupled to the system controller, and locks the destination when the destination is the local memory unit; a receiving unit which receives the access request from the output unit and an access request from an other system controller; a global snoop control unit which sends a response indicating whether the access request is executable or not, and controls locking of the destination of the access request when the destination is the local memory unit; and an access processing unit which unlocks the locking and accesses the memory unit when the access request from the access source becomes executable.

Abstract: A processor includes a first transmitting unit that transmits, when receiving from a second processor a transmission request indicating transmission of target data which is read from a main storage unit and stored in the first processor, a transfer instruction to the first processor, the transfer instruction indicating transfer of the target data and state information to the second processor, the state information indicating a state of the target data used when the second processor reads and stores the target data. The processor includes a second transmitting unit that transmits acquisition information indicating acquisition of the target data to the second processor before receiving a response to the transfer instruction transmitted by the first transmitting unit from the first processor.

Abstract: A processor is connected to a main storage device and includes a cache memory unit, a tag memory unit, a main storage control unit, a cache control unit, a main storage access monitoring unit, a cache access monitoring unit, and a swap control unit. The cache memory unit includes a plurality of cache lines. The tag memory unit includes a plurality of tags. The main storage control unit accesses the main storage device. The cache control unit accesses the cache memory unit. The main storage access monitoring unit monitors a first access frequency. The cache access monitoring unit monitors a second access frequency. The swap control unit allows the cache control unit to retain data in the main storage device based on the first access frequency, the second access frequency, and state information retained in a tag.

Abstract: An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended.

Abstract: A central processing unit, connected to a main memory among a plurality of central processing units each including a cache memory, includes a control unit. The control unit executes a process including: classifying the plurality of central processing units into a smaller number than a total number of the plurality of central processing units, and writing to the main memory presence information indicating whether or not the same data as data stored in the main memory is held in a cache memory included in any of the central processing units that belong to a corresponding central processing unit group, for each central processing unit group of a plurality of central processing unit groups obtained by the classifying.

Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Abstract: An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt.

Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Abstract: A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit.

Abstract: An information processing apparatus, a memory control method, and a memory control device are disclosed, the information processing apparatus including nodes each having a main memory, a processor including a cache memory, and a system controller. The system controller of at least one of the nodes includes a holding unit that holds address information corresponding to primary data stored in the main memory of its local node, and not cached in any of the cache memories of other nodes. The system controller of the at least one node may include local and global snoop control units, as well as a virtual tag expansion (VTAGx) unit, to maintain cache coherency, and under certain conditions, a snoop operation may be skipped or omitted.

Abstract: A system includes a first apparatus and a second apparatus connected via a transmission path. The first apparatus includes a transmitting unit that transmits a request as at least one packet and retransmits the at least one request packet if a time period between the request and a response is not less than a predetermined time period; and a receiving unit that receives the response as at least one response packet and discards any error packet and any redundant packet from among the received at least one response packet. The second apparatus includes: a receiving unit that receives the at least one request packet and discards any error packet from among the received at least one request packet; and a transmitting unit that determines a response type, selectively makes the at least one response packet redundant for any response of a specific type, and transmits the redundant response packets.

Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.

Abstract: One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory as well as controls a data transfer of at least one of the cache memory and the main memory by a memory access request, wherein each system controller including a snoop controller that selects a transfer source CPU from transfer source candidate CPUs each having cache memory including a data requested by the memory access request when the data is available in a plurality of cache memories.