Abstract: One aspect of the embodiments utilizes a system controller which has a broadcast transmitting and receiving unit that receives a memory access request from each of CPU and notifies to the other system controllers and a snoop control unit that judges when the memory access request from any of the CPUs for each of the cache memories in the CPU is received, whether object data conflicts with object data requested by a prior access request received earlier than the memory access request and whether the object data is present in any of the cache memories, selects the status of the cache memory of the CPU, notifies the other system controller of a snoop processing result in which the status selected and the cache memory are associated, and set a final status as the status of the system controller based on priority of each status of other system controllers.

Abstract: A system controller includes an output unit which transfers an access request from an access source coupled to the system controller to an other system controller; a local snoop control unit that determines whether a destination of the access request from the access source is a local memory unit coupled to the system controller, and locks the destination when the destination is the local memory unit; a receiving unit which receives the access request from the output unit and an access request from an other system controller; a global snoop control unit which sends a response indicating whether the access request is executable or not, and controls locking of the destination of the access request when the destination is the local memory unit; and an access processing unit which unlocks the locking and accesses the memory unit when the access request from the access source becomes executable.

Abstract: A data processing system includes a plurality of nodes connected with each other, each of the nodes including a processor and a memory, each of the processor including a processing unit, a cache memory, a tag memory for storing tag information, the processor accessing data to be processed, in the tag memory in reference to the tag information, and a cache controller for controlling saving or evacuating of data in the cache memory, the cache controller, checking if the data to be evacuated originated from the memory of its own node or from any other memory of any other node, and when the data to be evacuated originated from any other memory of any other node, storing the data into the memory of its own node at a particular address of the memory and storing information of the particular address in the tag memory as tag information.

Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.

Abstract: The present invention relates to an information processing apparatus equipped with a plurality of storage units and a plurality of system controllers sharing communication control on the plurality of storage units. For shortening the processing time needed for a memory access request, each of the plurality of system controllers includes a local snoop control unit for, when receiving the memory access request, retrieving target data on the memory access request from the storage unit, this system controller takes charge of, in parallel with transmission/reception processing on a retrieval instruction in a broadcast transmitting/receiving unit or processing in a global snoop control unit and a memory access control unit for fulfilling the memory access request when the target data is retrieved by the local snoop control unit and a predetermined condition reaches satisfaction.

Abstract: A system includes a first apparatus and a second apparatus connected via a transmission path. The first apparatus includes a transmitting unit that transmits a request as at least one packet and retransmits the at least one request packet if a time period between the request and a response is not less than a predetermined time period; and a receiving unit that receives the response as at least one response packet and discards any error packet and any redundant packet from among the received at least one response packet. The second apparatus includes: a receiving unit that receives the at least one request packet and discards any error packet from among the received at least one request packet; and a transmitting unit that determines a response type, selectively makes the at least one response packet redundant for any response of a specific type, and transmits the redundant response packets.

Abstract: The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved.

Abstract: A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache, includes a consumption determining unit that monitors a consumption status of a hardware resource used in the speculative fetch, and determines whether a consumption of the hardware resource exceeds a predetermined value; and a speculative-fetch issuing unit that stops issuing the speculative fetch when the consumption determining unit determines that the consumption of the hardware resource exceeds the predetermined value.

Abstract: One aspect of the embodiments utilizes an information processing apparatus having a plurality of system boards connected via a bus, each system board including a CPU having a cache memory, a main memory that forms a shared memory, and a system controller that manages the CPU and the main memory as well as controls a data transfer of at least one of the cache memory and the main memory by a memory access request, wherein each system controller including a snoop controller that selects a transfer source CPU from transfer source candidate CPUs each having cache memory including a data requested by the memory access request when the data is available in a plurality of cache memories.

Abstract: One aspect of the embodiments utilizes a system controller which has a broadcast transmitting and receiving unit that receives a memory access request from each of CPU and notifies to the other system controllers and a snoop control unit that judges when the memory access request from any of the CPUs for each of the cache memories in the CPU is received, whether object data conflicts with object data requested by a prior access request received earlier than the memory access request and whether the object data is present in any of the cache memories, selects the status of the cache memory of the CPU, notifies the other system controller of a snoop processing result in which the status selected and the cache memory are associated, and set a final status as the status of the system controller based on priority of each status of other system controllers.

Abstract: A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received externally and reoutputs it in response to an error retry instruction. A broadcast output section broadcasts the memory access request. A broadcast input section receives the broadcast memory access request. A global port holds the received memory access request. A snoop control section transmits and receives cache status information containing a result of snooping, and detects a synchronization error on the basis of the cache status information. If a synchronization error occurs, the snoop control section outputs the error retry instruction to the local port holding the memory access request that resulted in the synchronization error.

Abstract: A system control apparatus and method capable of increasing the possibility of recovery from a synchronization error in snooping between system controllers are provided. The system control apparatus has a local port that holds a memory access request received externally and reoutputs it in response to an error retry instruction. A broadcast output section broadcasts the memory access request. A broadcast input section receives the broadcast memory access request. A global port holds the received memory access request. A snoop control section transmits and receives cache status information containing a result of snooping, and detects a synchronization error on the basis of the cache status information. If a synchronization error occurs, the snoop control section outputs the error retry instruction to the local port holding the memory access request that resulted in the synchronization error.

Abstract: In a memory controller such as a system controller including a level-3 cache memory for common use of data with a level-2 cache memory within a CPU by forming a chip set such as a server, an effective memory controller and a control method are realized to store the necessary data into the level-2 cache memory of the CPU with a single access, thereby reducing or eliminating deterioration of performance and suppression of throughput caused by memory latency.

Abstract: The present invention relates to an information processing apparatus equipped with a plurality of storage units and a plurality of system controllers sharing communication control on the plurality of storage units. For shortening the processing time needed for a memory access request, each of the plurality of system controllers includes a local snoop control unit for, when receiving the memory access request, retrieving target data on the memory access request from the storage unit, this system controller takes charge of, in parallel with transmission/reception processing on a retrieval instruction in a broadcast transmitting/receiving unit or processing in a global snoop control unit and a memory access control unit for fulfilling the memory access request when the target data is retrieved by the local snoop control unit and a predetermined condition reaches satisfaction.

Abstract: A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache, includes a consumption determining unit that monitors a consumption status of a hardware resource used in the speculative fetch, and determines whether a consumption of the hardware resource exceeds a predetermined value; and a speculative-fetch issuing unit that stops issuing the speculative fetch when the consumption determining unit determines that the consumption of the hardware resource exceeds the predetermined value.