Abstract: An electronic device is provided. The electronic device includes a display that is configured to show content that includes a plurality of frames. The plurality of frames includes a first frame that is associated with a pre-transition value. The plurality of frames also includes a second frame that is associated with a current frame value that corresponds to a first luminance. Additionally, the electronic device is configured to determine an overdriven current frame value corresponding to a second luminance that is greater than the first luminance. The electronic device is also configured to display the second frame using the overdriven current frame value.

Abstract: The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor.

Abstract: The disclosed concepts provide a method to generate and use a compound shader object. A compound shader object includes a shader's intermediate representation (IR) and one or more binary modules; each binary module configured to execute on one type of graphics processing unit (GPU) with a specific input state. One method includes receiving, through a public application programming interface (API), a request to execute a shader from an user-level application. At the framework level, if the request corresponds to one of the prior compiled binary modules, that module may be passed to a GPU for immediate execution via a system private interface. If the request does not correspond to one of the binary modules, the shader's IR module may returned to the requesting user-level application (which module would then have to be compiled before it may be sent to the GPU).

Abstract: Techniques are disclosed relating to flushing cache lines. In some embodiments, a graphics processing unit includes a cache and one or more storage elements configured to store a plurality of command buffers that include instructions executable to manipulate data stored in the cache. In some embodiments, ones of the cache lines in the cache are configured to store data to be operated on by instructions in the command buffers and a first tag portion that identifies a command buffer that has stored data in the cache line. In some embodiments, the graphics processing unit is configured to receive a request to flush cache lines that store data of a particular command buffer, and to flush ones of the cache lines having first tag portions indicating the particular command buffer as having data stored in the cache lines while maintaining data stored in other ones of the cache lines as valid.

Abstract: In various embodiments, hardware resources of a processing circuit may be allocated to a plurality of processes based on priorities of the processes. A hardware resource utilization sensor may detect a current utilization of the hardware resources by a process. A utilization accumulation circuit may determine a utilization of the hardware resources by the process over a particular amount of time. A target utilization of the hardware resources for the process may be determined based on the utilization of the hardware resources over the particular amount of time. A comparator circuit may compare the current utilization to the target utilization. A process priority adjustment circuit may adjust a priority of the process based on the comparison. Based on the adjusted priority, a different amount of hardware resources may be allocated to the processes.

Abstract: In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

Abstract: One disclosed embodiment is directed to graphics processing method for displaying a user interface. The method includes executing a plurality of graphic processing operation in a single rendering pass. The rendering pass includes several render targets. At least one of the render targets is designated as a memory-less render target. The memory-less render target is used to store intermediate data. The intermediate data is combined with the outcome of at least one other graphics processing operation to generate a combined result. The combined result is stored in the frame buffer memory for display.

Abstract: One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.

Abstract: Techniques for managing components of a processing system are described. Illustrative components include graphics processing units (GPUs), central processing units (CPUs), communication fabrics, memory controllers, or peripheral control circuits. For one embodiment, a performance control logic/module obtains information associated with components of a system during performance of a task by the system. The logic/module can determine the need to adjust an operational performance of a first component based on the obtained information. The performance control logic/module can also evaluate the obtained information to determine that the operational performance of one or more second components of the system should be adjusted to satisfy the determined need (of the first component). Moreover, the logic/module can adjust a first clock signal affecting the operational performance of the first component and one or more second clock signals affecting the operational performance of the one or more second components.

Abstract: Power management techniques are disclosed for a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

Abstract: Methods, systems and devices are disclosed to examine developer supplied graphics code and attributes at run-time. The graphics code designed for execution on a graphics processing unit (GPU) utilizing a coding language such as OpenCL or OpenGL which provides for run-time analysis by a driver, code generator, and compiler. Developer supplied code and attributes can be analyzed and altered based on the execution capabilities and performance criteria of a GPU on which the code is about to be executed. In general, reducing the number of developer defined work items or work groups can reduce the initialization cost of the GPU with respect to the work to be performed and result in an overall optimization of the machine code. Manipulation code can be added to adjust the supplied code in a manner similar to unrolling a loop to improve execution performance.

Abstract: In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

Abstract: Techniques are provided for managing the power consumption and performance of a processing device. Power consumption and utilization ratios for a processing device may be continuously measured. The measured power consumption and utilization ratios may be compared to target power consumption and utilization ratios to adjust an operating frequency of the processing device. In one implementation a power controller may take the target and measured power consumption as inputs to generate a power output and a utilization controller may take the target and measured utilization ratios as inputs to generate a utilization output. The lower of the power output and the utilization output may be selected and used to adjust the operating frequency of the processing device. The power and utilization controllers may implement a proportional-integral control scheme.

Abstract: A message exchange system for software components on different processors. A first component's attempt to load a write register with a message pointer (or a message itself) triggers a determination whether space exists in a shared memory queue. If so, the queue is updated by incrementing a message counter, writing the message/pointer into the queue where designated by a write pointer, and changing the write pointer to a next queue location. A second component's attempt to load the message/pointer from a read register triggers a determination whether there is at least one new message in the queue. If so, the queue is updated by decrementing the message counter, reading the message/pointer from the queue where designated by a read pointer, and changing the read pointer to point to a next queue location. The determinations and queue updates are performed atomically with respect to the software components.

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Additionally, in some cases, it may be a better power/performance tradeoff to run the processor at a higher power/performance state if the processor is executing for a significant portion of the execution interval (e.g. the frame time for a GPU). Executing at a higher power/performance state may permit a realization of a greater number of frames per second for a given workload, in an embodiment.

Abstract: Methods, systems and devices are disclosed to examine developer supplied graphics code and attributes at run-time. The graphics code designed for execution on a graphics processing unit (GPU) utilizing a coding language such as OpenCL or OpenGL which provides for run-time analysis by a driver, code generator, and compiler. Developer supplied code and attributes can be analyzed and altered based on the execution capabilities and performance criteria of a GPU on which the code is about to be executed. In general, reducing the number of developer defined work items or work groups can reduce the initialization cost of the GPU with respect to the work to be performed and result in an overall optimization of the machine code. Manipulation code can be added to adjust the supplied code in a manner similar to unrolling a loop to improve execution performance.

Abstract: An innovative GPU framework and related APIs present more accurate representations of the target hardware so that the distinctions between the fixed-function and programmable features of the GPU are perceived by a developer. This permits a program and/or a graphics object generated or manipulated by the program to be understood as not just code, but machine states that are associated with the code. When such an object is defined, the definitional components requiring programmable GPU features can be compiled only once and reused repeatedly as needed. Similarly, when a state change is made, the state changes correspond to the state changes made on the hardware. Additionally, the creation of these immutable objects prevents a developer from inadvertently changing portions of the program or object that cause it to behave differently than intended.

Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.

Abstract: A plurality of asynchronous command streams are established. A first command stream shares a common resource with a second command stream. A synchronization object is incorporated into the first command stream. A central server arbitrates serialization of the first and second command streams using the synchronization object. The central server arbitrates serialization without direct communication between the first and second command streams.

Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.