Abstract: In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).

Abstract: Techniques are provided for managing the power consumption and performance of a processing device. Power consumption and utilization ratios for a processing device may be continuously measured. The measured power consumption and utilization ratios may be compared to target power consumption and utilization ratios to adjust an operating frequency of the processing device. In one implementation a power controller may take the target and measured power consumption as inputs to generate a power output and a utilization controller may take the target and measured utilization ratios as inputs to generate a utilization output. The lower of the power output and the utilization output may be selected and used to adjust the operating frequency of the processing device. The power and utilization controllers may implement a proportional-integral control scheme.

Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.

Abstract: A method of displaying a user interface in a portable electronic device is provided. The method includes displaying a user interface via a graphics layer attached to a software renderer, detaching the graphics layer from the software renderer, and attaching the graphics layer to one or more of a plurality of hardware layers, such that the display of the graphics layer is facilitated by one or more features of at least one of the hardware layers. An electronic device is provided that includes a display, a processor coupled to the display and configured to provide a plurality of hardware layers, and a user interface comprising a graphics layer, wherein the display of the graphics layer is facilitated by one or more features of at least one of the hardware layers, wherein the graphics layer dynamically attaches to or detaches from one or more of the plurality of hardware layers.

Abstract: Methods and system for sharing a hardware resource in a computer system running at least one software process having multiple threads. A lock_indicator is provided in data structures within the computer system. A request is received to use the hardware resource by one of the threads that is defined to be a requesting tread. Based on the lock_indicator, it is determined whether the hardware resource is available for use by the requesting thread. If this indicates that the hardware resource is available, the lock_indicator is set under control of the hardware resource to instead indicate that the hardware resource is unavailable, and a go_indicator signals to indicate that use of the hardware resource for the request can now proceed.

Abstract: A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Additionally, in some cases, it may be a better power/performance tradeoff to run the processor at a higher power/performance state if the processor is executing for a significant portion of the execution interval (e.g. the frame time for a GPU). Executing at a higher power/performance state may permit a realization of a greater number of frames per second for a given workload, in an embodiment.

Abstract: The described embodiments comprise a system that adjusts pixel values to produce visual effects in a frame to be displayed. During operation, the system receives coordinates and pixel-adjustment values for one or more control points within the frame. Next, the system calculates pixel-adjustment values for pixels in the frame based on the coordinates and the pixel-adjustment values for the one or more control points. The system then applies the pixel-adjustment values to the pixels within the frame and displays the frame.

Abstract: A plurality of asynchronous command streams are established. A first command stream shares a common resource with a second command stream. A synchronization object is incorporated into the first command stream. A central server arbitrates serialization of the first and second command streams using the synchronization object. The central server arbitrates serialization without direct communication between the first and second command streams.

Abstract: A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.

Abstract: A display driving architecture that can include two graphics pipelines with an optional connection between them to provide a mirrored mode. In one embodiment, one of the two pipelines can be automatically configured (e.g. routed in one of a plurality of ways, such as routing to do color conversion) based upon the type of cable that is coupled to a connector of the one pipeline. In another embodiment, a connection of a cable can cause display information (e.g. resolutions of an external display) to be provided to an application which can select a display mode while one of the graphics pipelines is kept in a low power state.

Abstract: Improved techniques and systems for electronic delivery of digital media asset files to electronic devices are disclosed. In one embodiment, a media item can be stored in a multi-part media item file. The multi-part media item file for the media item can be delivered to a host device that can thereafter support a plurality of different media presentation devices that have different media presentation capabilities. The host device can distribute customized (or optimized) versions of the multi-part media item file to different media presentation devices. In one embodiment, the multi-part media item file can include at least a plurality of video streams. When the media item is to be presented by one of the media presentation devices, the media presentation device can decode the plurality of video streams from the multi-part media item file into decoded video frames and then combine the decoded video frames from the different streams for presentation of video of the media item.

Abstract: Systems and methods are discussed for performing 3D animation of an object using limited hardware resources. When an object is rotated, the size of the object displayed progressively increases, thus taking up more memory, CPU, and other hardware resources. To limit the impact on resources as an object becomes larger, the electronic device may select to display more small frames of the object at a higher frame rate, and fewer large frames at a lower frame rate, thus providing a uniform 3D animation.

Abstract: A technique is provided for animating an image or a portion of an image. In accordance with this technique, intermediary or transitional images, referred to as offset images, are displayed as part of an animation step to lessen abrupt changes in pixel values. In one embodiment, the offset images are generated using a weighted average of proximate pixels. In such an embodiment, the weight factor may take into account the distance of the offset from the proximate pixels such that closer pixels are more heavily weighted. Based on the direction of movement for the animation, the offset images are ordered and displayed as part of the animation steps of an animation sequence.

Abstract: A method of displaying a user interface in a portable electronic device is provided. The method includes displaying a user interface via a graphics layer attached to a software renderer, detaching the graphics layer from the software renderer, and attaching the graphics layer to one or more of a plurality of hardware layers, such that the display of the graphics layer is facilitated by one or more features of at least one of the hardware layers. An electronic device is provided that includes a display, a processor coupled to the display and configured to provide a plurality of hardware layers, and a user interface comprising a graphics layer, wherein the display of the graphics layer is facilitated by one or more features of at least one of the hardware layers, wherein the graphics layer dynamically attaches to or detaches from one or more of the plurality of hardware layers.

Abstract: A system that adjusts pixel values to produce visual effects in a frame to be displayed is presented. During operation, the system receives coordinates and pixel-adjustment values for one or more control points within the frame. Next, the system calculates pixel-adjustment values for pixels in the frame based on the coordinates and the pixel-adjustment values for the one or more control points. The system then applies the pixel-adjustment values to the pixels within the frame and displays the frame.

Abstract: A message exchange system for software components on different processors. A first component's attempt to load a write register with a message pointer (or a message itself) triggers a determination whether space exists in a shared memory queue. If so, the queue is updated by incrementing a message counter, writing the message/pointer into the queue where designated by a write pointer, and changing the write pointer to a next queue location. A second component's attempt to load the message/pointer from a read register triggers a determination whether there is at least one new message in the queue. If so, the queue is updated by decrementing the message counter, reading the message/pointer from the queue where designated by a read pointer, and changing the read pointer to point to a next queue location. The determinations and queue updates are performed atomically with respect to the software components.

Abstract: Methods and system for sharing a hardware resource in a computer system running at least one software process having multiple threads. A lock_indicator is provided in data structures within the computer system. A request is received to use the hardware resource by one of the threads that is defined to be a requesting tread. Based on the lock_indicator, it is determined whether the hardware resource is available for use by the requesting thread. If this indicates that the hardware resource is available, the lock_indicator is set under control of the hardware resource to instead indicate that the hardware resource is unavailable, and a go_indicator signals to indicate that use of the hardware resource for the request can now proceed.