Patents by Inventor GONG OUYANG

GONG OUYANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11903138
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • Publication number: 20210352807
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • Patent number: 11089689
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: August 10, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • Patent number: 10304593
    Abstract: A data carrying cable to connect computing devices includes a first cable portion including a first conductor having a circular cross-section and a first gauge. A first port connector is connected to one end of the first cable portion. A second cable portion includes a second conductor having a circular cross-section and a second gauge that is different than the first gauge. The first conductor and the second conductor are arranged in series and are configured to carry a data signal between the computing devices.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: May 28, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Gong Ouyang, Mark A. Shaw, Alexander Levin, Martha Geoghegan Peterson
  • Publication number: 20190122789
    Abstract: A data carrying cable to connect computing devices includes a first cable portion including a first conductor having a circular cross-section and a first gauge. A first port connector is connected to one end of the first cable portion. A second cable portion includes a second conductor having a circular cross-section and a second gauge that is different than the first gauge. The first conductor and the second conductor are arranged in series and are configured to carry a data signal between the computing devices.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Gong Ouyang, Mark A. Shaw, Alexander Levin, Martha Geoghegan Peterson
  • Patent number: 10249924
    Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 2, 2019
    Assignee: INTEL CORPORATION
    Inventors: Kai Xiao, Raul Enriquez Shibayama, Gong Ouyang, Jose Diego Guillen Gonzalez, Beom-Taek Lee
  • Publication number: 20190098764
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.
    Type: Application
    Filed: April 2, 2016
    Publication date: March 28, 2019
    Applicant: INTEL CORPORATION
    Inventors: ERIC LI, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • Patent number: 10128591
    Abstract: One embodiment provides an electrical connector. The electrical connector includes a housing defining a slot; and a pin. The pin includes a stub member comprising a first portion and a second portion, the first portion to couple to a first printed circuit board; and a movable member operable to engage the second portion of the stub member to create a conductive path, wherein the stub member is only engaged with the movable member when a second printed circuit board is inserted into the slot.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Gong Ouyang, Kai Xiao, Lu-Vong T. Phan
  • Publication number: 20180174940
    Abstract: Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Applicant: Intel Corporation
    Inventors: Shelby Ferguson, Gong Ouyang, Russell S. Aoki, Zhichao Zhang, Kai Xiao
  • Patent number: 9935036
    Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Gong Ouyang, Beom-Taek Lee
  • Patent number: 9935353
    Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Gong Ouyang, Shaowu Huang, Kai Xiao
  • Patent number: 9922751
    Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Eric J. Li, Kemal Aygun
  • Patent number: 9894752
    Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Kemal Aygun, Beom-Taek Lee
  • Patent number: 9791899
    Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 17, 2017
    Assignee: INTEL CORPORATION
    Inventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
  • Publication number: 20170287591
    Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Eric J. Li, Kemal Aygun
  • Publication number: 20170207146
    Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 26, 2015
    Publication date: July 20, 2017
    Inventors: GONG OUYANG, BEOM-TAEK LEE
  • Publication number: 20170168528
    Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
    Type: Application
    Filed: December 14, 2015
    Publication date: June 15, 2017
    Inventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
  • Publication number: 20170086288
    Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Gong Ouyang, Shaowu Huang, Kai Xiao
  • Publication number: 20170069988
    Abstract: One embodiment provides an electrical connector. The electrical connector includes a housing defining a slot; and a pin. The pin includes a stub member comprising a first portion and a second portion, the first portion to couple to a first printed circuit board; and a movable member operable to engage the second portion of the stub member to create a conductive path, wherein the stub member is only engaged with the movable member when a second printed circuit board is inserted into the slot.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Applicant: Intel Corporation
    Inventors: GONG OUYANG, KAI XIAO, LU-VONG T. PHAN
  • Publication number: 20160378215
    Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Kai Xiao, Raul Enriquez Shibayama, Gong Ouyang, Jose Diego Guillen Gonzalez, Beom-Taek Lee