Patents by Inventor GONG OUYANG
GONG OUYANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903138Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.Type: GrantFiled: July 22, 2021Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
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Publication number: 20210352807Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Applicant: INTEL CORPORATIONInventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
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Patent number: 11089689Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.Type: GrantFiled: April 2, 2016Date of Patent: August 10, 2021Assignee: INTEL CORPORATIONInventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
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Patent number: 10304593Abstract: A data carrying cable to connect computing devices includes a first cable portion including a first conductor having a circular cross-section and a first gauge. A first port connector is connected to one end of the first cable portion. A second cable portion includes a second conductor having a circular cross-section and a second gauge that is different than the first gauge. The first conductor and the second conductor are arranged in series and are configured to carry a data signal between the computing devices.Type: GrantFiled: October 20, 2017Date of Patent: May 28, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Gong Ouyang, Mark A. Shaw, Alexander Levin, Martha Geoghegan Peterson
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Publication number: 20190122789Abstract: A data carrying cable to connect computing devices includes a first cable portion including a first conductor having a circular cross-section and a first gauge. A first port connector is connected to one end of the first cable portion. A second cable portion includes a second conductor having a circular cross-section and a second gauge that is different than the first gauge. The first conductor and the second conductor are arranged in series and are configured to carry a data signal between the computing devices.Type: ApplicationFiled: October 20, 2017Publication date: April 25, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Gong Ouyang, Mark A. Shaw, Alexander Levin, Martha Geoghegan Peterson
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Patent number: 10249924Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.Type: GrantFiled: June 26, 2015Date of Patent: April 2, 2019Assignee: INTEL CORPORATIONInventors: Kai Xiao, Raul Enriquez Shibayama, Gong Ouyang, Jose Diego Guillen Gonzalez, Beom-Taek Lee
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Publication number: 20190098764Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.Type: ApplicationFiled: April 2, 2016Publication date: March 28, 2019Applicant: INTEL CORPORATIONInventors: ERIC LI, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
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Patent number: 10128591Abstract: One embodiment provides an electrical connector. The electrical connector includes a housing defining a slot; and a pin. The pin includes a stub member comprising a first portion and a second portion, the first portion to couple to a first printed circuit board; and a movable member operable to engage the second portion of the stub member to create a conductive path, wherein the stub member is only engaged with the movable member when a second printed circuit board is inserted into the slot.Type: GrantFiled: September 8, 2015Date of Patent: November 13, 2018Assignee: Intel CorporationInventors: Gong Ouyang, Kai Xiao, Lu-Vong T. Phan
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Publication number: 20180174940Abstract: Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.Type: ApplicationFiled: December 19, 2016Publication date: June 21, 2018Applicant: Intel CorporationInventors: Shelby Ferguson, Gong Ouyang, Russell S. Aoki, Zhichao Zhang, Kai Xiao
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Patent number: 9935036Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.Type: GrantFiled: June 26, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Gong Ouyang, Beom-Taek Lee
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Patent number: 9935353Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.Type: GrantFiled: September 23, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Gong Ouyang, Shaowu Huang, Kai Xiao
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Patent number: 9922751Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.Type: GrantFiled: April 1, 2016Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Eric J. Li, Kemal Aygun
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Patent number: 9894752Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.Type: GrantFiled: April 3, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Kemal Aygun, Beom-Taek Lee
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Patent number: 9791899Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.Type: GrantFiled: December 14, 2015Date of Patent: October 17, 2017Assignee: INTEL CORPORATIONInventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
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Publication number: 20170287591Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Eric J. Li, Kemal Aygun
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Publication number: 20170207146Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 26, 2015Publication date: July 20, 2017Inventors: GONG OUYANG, BEOM-TAEK LEE
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Publication number: 20170168528Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Gong Ouyang, Kai Xiao, Lu-Vong Phan
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Publication number: 20170086288Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Gong Ouyang, Shaowu Huang, Kai Xiao
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Publication number: 20170069988Abstract: One embodiment provides an electrical connector. The electrical connector includes a housing defining a slot; and a pin. The pin includes a stub member comprising a first portion and a second portion, the first portion to couple to a first printed circuit board; and a movable member operable to engage the second portion of the stub member to create a conductive path, wherein the stub member is only engaged with the movable member when a second printed circuit board is inserted into the slot.Type: ApplicationFiled: September 8, 2015Publication date: March 9, 2017Applicant: Intel CorporationInventors: GONG OUYANG, KAI XIAO, LU-VONG T. PHAN
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Publication number: 20160378215Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Kai Xiao, Raul Enriquez Shibayama, Gong Ouyang, Jose Diego Guillen Gonzalez, Beom-Taek Lee