Patents by Inventor GONG OUYANG

GONG OUYANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160276091
    Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
    Type: Application
    Filed: March 21, 2015
    Publication date: September 22, 2016
    Applicant: INTEL CORPORATION
    Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Kemal Aygun, Beom-Taek Lee
  • Publication number: 20160276092
    Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
    Type: Application
    Filed: April 3, 2015
    Publication date: September 22, 2016
    Applicant: Intel Corporation
    Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Kemal Aygun, Beom-Taek Lee
  • Patent number: 9338882
    Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Kai Xiao, Raul Enriquez Shibayama, Gong Ouyang
  • Patent number: 9318850
    Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Xiang Li, Hao-Han Hsu, Yun Ling, Gong Ouyang, Kai Xiao, Jiangqi He, Lu-Vong T. Phan, Wei Xu
  • Publication number: 20150340817
    Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: Xiang Li, Hao-Han Hsu, Yun Ling, Gong Ouyang, Kai Xiao, Jiangqi He, Lu-Vong T. Phan, Wei Xu
  • Publication number: 20150333387
    Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 19, 2015
    Inventors: KAI XIAO, RAUL ENRIQUEZ SHIBAYAMA, GONG OUYANG