Abstract: Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The semiconductor structure formation method includes: providing a substrate, the substrate including a contact region and a virtual region arranged adjacent to each other, a bitline structure and a dielectric layer arranged discretely being formed on the substrate, an extension direction of the dielectric layer intersecting with that of the bitline structure, and the bitline structure and the dielectric layer defining discrete capacitor contact openings; forming a sacrificial layer filling the capacitor contact opening; removing, in the contact region, the sacrificial layer to form a second opening; forming a bottom conductive layer filling the second opening; removing, in the virtual region, some height of the sacrificial layer to form a first opening; forming an insulation layer filling the first opening; and forming a capacitor contact structure located in the second opening.

Abstract: Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The method includes: the substrate including contact region and dummy region, a first bitline structure and a first dielectric layer being formed on the substrate, the first bitline structure and the first dielectric layer defining discrete capacitor contact openings; forming a first sacrificial layer filling the capacitor contact opening; removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer; forming an insulation layer filling the first opening; removing, in the contact region, the first sacrificial layer to form a second opening; and forming a capacitor contact structure located in the second opening.

Abstract: The disclosure relates to a buried bit line and a forming method thereof, the buried bit line is formed in a bit line slot of a substrate, the buried bit line includes a first bit line layer formed in the bit line slot, a first blocking layer and a second bit line layer. A top of the first bit line layer is lower than a surface of the substrate. The first blocking layer is at least partially formed between the first bit line layer and an inner wall of the bit line slot. The second bit line layer is formed in the bit line slot and configured to communicate the first bit line layer with a drain region in the substrate.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes: a base including an array region and a peripheral region, the peripheral region having a first isolation structure, the array region having a second isolation structure, a top opening area of the first isolation structure being greater than that of the second isolation structure; the first isolation structure having a first groove, and a first insulation structure configured to fill the first groove; and the first insulation structure including at least a top isolation layer, a top surface of the top isolation layer being flush with a top surface of the base, and the top isolation layer being made of at least a low dielectric constant material.

Abstract: A method for manufacturing a buried word line transistor can include the following operations. A semiconductor substrate having an active region is provided. A first trench is formed in the active region. A first insulation layer is formed on a side wall of the first trench. A bottom portion of the first trench is etched to form a second trench. A gate oxide layer is formed on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench. A barrier layer is formed at a bottom portion and portion of a side wall of the gate oxide layer. A metal filler layer is formed on an inner side of the barrier layer. The first insulation layer is removed to form a side trench. A second insulation layer is formed at a top end of the side trench. A sealed air spacer layer is formed.

Abstract: A method for preparing a semiconductor structure includes: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first insulation layer, the first insulation layer at least covering an inner wall of the groove; forming a channel layer, the channel layer at least covering an inner wall of the first insulation layer; forming a second insulation layer, the second insulation layer at least covering an inner wall of the channel layer; filling the groove with a word line structure; removing part of the semiconductor substrate, part of the first insulation layer, and part of the channel layer, and forming a recess region in an outer side wall of the second insulation layer; and forming a source-drain in the recess region, the source-drain being electrically connected with the channel layer.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate, a trench and a word line. The substrate includes an isolation structure and an active area. The active area includes irons of a first type. The trench is arranged in the active area, an inner surface of the trench includes an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer is arranged above the oxide layer. The word line is arranged in the trench. The inversion doping layer includes ions of a second type. The first type is contrary to the second type.

Abstract: A semiconductor structure includes a substrate, a bit line, and a first isolation layer. A groove is set in the substrate. A bottom end of the bit line is set in the groove. The first isolation layer is at least partially set on a sidewall of the bit line, and the first isolation layer is in direct contact with the bit line.

Abstract: A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures.

Abstract: A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.

Abstract: A method for preparing a semiconductor device includes the following operations. A semiconductor substrate is provided, and a gate dielectric layer, a first conductive layer, and a support layer with a through hole are sequentially formed on the semiconductor substrate. A barrier layer and a second conductive layer are formed in the through hole. The support layer and a part of the first conductive layer located below the support layer are removed to form a primary gate pattern and expose the gate dielectric layer. A gate sidewall protective layer is formed on a sidewall of the primary gate pattern. An insulating layer is formed on a top of the primary gate pattern, a surface of the gate sidewall protective layer and a surface of the exposed part of the gate dielectric layer. A part of the insulating layer and a part of the gate dielectric layer are removed.