Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.

Abstract: A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

Abstract: An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage V3; and a fourth portion during which it remains fixed at V3. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that V2 is maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

Abstract: An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage V3; and a fourth portion during which it remains fixed at V3. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that V2 is maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

Abstract: A substantially symmetric inductor comprising a plurality of windings, at least one conductor crossover, and a peripheral conductor disposed at the periphery of the plurality of windings, the plurality of windings having a generally symmetric shape, each of the plurality of windings having a center and being of a different size from other ones of the plurality of windings, the peripheral conductor being generally symmetric and having a center, the plurality of windings and the peripheral conductor being substantially concentric, the conductor crossovers being disposed such that the symmetry of the inductor in substantially preserved. A method of winding an inductor such that the inductor is substantially symmetric about a center of the inductor, whereby signal degradation due to asymmetry of the inductor is substantially minimized.

Abstract: A bipolar transistor-based linearizer with programmable gain and phase response apparatus uses a splitter to separate an incoming RF signal into two equal components: in-phase (I) and quadrature (Q, ninety degrees delayed). The I signal then passes through a first bipolar variable gain amplifier (VGA) while the Q signal passes through a second bipolar VGA. After passing through the first and second VGAs, the amplified signals are combined at the output using a summer to produce a predistorted signal that drives a TWTA. The gains of each VGA are controlled using an RF power detector in conjunction with a bipolar gain/phase slope controller. Each gain can be adjusted separately to product a large range of linearization characteristics.

Abstract: An effective means and apparatus for generating a negative resistance including a circuit element that exhibits an increase in current as the applied voltage is decreased. Other embodiments of the present invention provide electronic means for improving the quality Q factor of on-chip resonators, which enables the creation of high-performance bipolar RF circuits with a minimum of external components.

Abstract: A bipolar transistor-based linearizer with programmable gain and phase response apparatus uses a splitter to separate an incoming RF signal into two equal components: in-phase (I) and quadrature (Q, ninety degrees delayed). The I signal then passes through a first bipolar variable gain amplifier (VGA) while the Q signal passes through a second bipolar VGA. After passing through the first and second VGAs, the amplified signals are combined at the output using a summer to produce a predistorted signal that drives a TWTA. The gains of each VGA are controlled using an RF power detector in conjunction with a bipolar gain/phase slope controller. Each gain can be adjusted separately to product a large range of linearization characteristics.

Abstract: An effective means and apparatus for generating a negative resistance including a circuit element that exhibits an increase in current as the applied voltage is decreased. Other embodiments of the present invention provide electronic means for improving the quality Q factor of on-chip resonators, which enables the creation of high-performance bipolar RF circuits with a minimum of external components.

Abstract: An apparatus and method of improving linearity of a multi bit &Dgr;&Sgr; modulator in which the output of a multi-bit quantizer of a &Dgr;&Sgr; modulator is connected in a feedback loop to a converter where output is a higher frequency single bit data stream which is supplied to a 1-bit digital to analog converter whose output is fed back to the quantizer to provide linearity of the output of the &Dgr;&Sgr; modulator.

Abstract: Several delta-sigma modulator circuits and a single quantizer provide analog-to-digital conversion for multiple frequency bands. A wideband mode is provided by coupling an analog signal to be digitized directly to a quantizer. Narrowband modes are provided by switching the analog signal to be digitized into one of several delta-sigma modulator circuits. Noise shaping and filtering by the delta-sigma modulator circuits result in improved signal-to-noise-and-distortion performance and increased resolution. Performance is further enhanced by feeding back multiple bits output by the quantizer to the delta-sigma modulator circuits. The delta-sigma modulator circuits can be either continuous time or discrete time delta sigma modulators.

Abstract: A method to design and fabricate circuits is disclosed which will permit such circuits to operate at higher frequencies. The method is particularly adapted to integrated digital circuits, and to differential sections of such circuits, but may be applied more broadly. A load on the output of an amplifying section of the circuit is designed employing a section of high impedance inductive transmission line nearest the output node, which is then connected to a section of low impedance capacitive transmission line, and then is terminated into a resistor which provides the 0 Hz load for the circuit. By reducing the effect of the resistor portion of the load, the capacitive transmission line section permits the entire load, as seen at the output of the amplifying section, to appear more ideally inductive than has previously been achieved. Due to this inductive appearance, response times are improved and the circuit is able to operate at significantly higher frequencies.

Abstract: Processing apparatus is provided that directly samples and quantizes a complex envelope of a bandlimited waveform centered at a predetermined carrier frequency. An oversampling delta-sigma modulator 1 samples and quantizes the input signal to a single bit data stream. A serial-to-parallel converter converts the single bit data stream into a parallel bit stream. A digital decimation filter digitally filters the parallel bit stream to produce an estimate of the baseband in-phase and quadrature components of the input signal. In-phase and quadrature video filters generate in-phase and quadrature samples that are output from the analog signal converter. A controller 26 and a plurality of digital-to-analog converters 25 are used to center noise shaping nulls of the delta-sigma modulator around the carrier frequency. The controller sets the spacing between nulls of the serial-to-parallel converter to maximize the signal-to-noise ratio of the analog signal.

Abstract: A digital waveform generator reads out simulated .DELTA..SIGMA. ADC data for a desired periodic analog waveform from a memory and converts it, using a low-resolution high speed DAC, into a synthesized analog waveform. The .DELTA..SIGMA. digital waveform generator is preferably designed to take advantage of the natural evolution of device technologies. The memory is fabricated with older technologies, which tend to be slower but have a much higher integration. The DAC is implemented in more recent technologies, which are faster but have less integration. A speed up buffer or buffers in intermediate speed intermediate integration technologies may be included to provide a bridge between the low speed memory and the low integration DAC.

Abstract: A positive current source (PCS) for supplying common mode current. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply the common mode current (I.sub.cm) while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity. The PCS has a common mode resistance which is small enough to maintain a stable common mode operating point with process variations providing minimal impact.

Abstract: A differential nonlinear transmission line (NLTL) circuit has anti-parallel diode pairs along a balanced transmission line to generate well defined high-speed pulses with sharp positive and negative transitions from a time varying input signal. The input signal may carry an arbitrary DC bias voltage component that is suitable for digital logic circuits, such as current mode logic (CML) employing differential inputs.

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Abstract: A continuous-time tunable Gm-C architecture for a .DELTA..SIGMA. modulator includes a tunable resonator and a low bit rate, high sample rate quantizer connected in a feedback loop. The resonator shapes the quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. A tunable Gm cell tunes the resonator's resonant frequency to maximize the modulator's SNR. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and a recombination circuit that together effectively multiply G.sub.f by a factor .alpha., where -1<=.alpha.<=1, without effecting the cell's common mode current I.sub.cm. A positive current source supplies I.sub.cm, while maintaining a common mode resistance of R/2 and a theoretically infinite differential mode resistance. Thus, the resonator's resonant frequency can be varied from DC to approximately 1 Ghz while maintaining a stable common mode operating point and improving the modulator's quality factor.

Abstract: An active filter circuit component includes an all NPN bipolar tunable Gm cell and a positive current source (PCS) for supplying common mode current. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and recombination circuit that together effectively multiply G.sub.f by a tuning factor .alpha., where -1.ltoreq..alpha..ltoreq.1, without effecting the cell's common mode current I.sub.cm. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply I.sub.cm, while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity.

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.