Patents by Inventor Gopal Raghavan

Gopal Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10732700
    Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 4, 2020
    Assignee: Eta Compute, Inc.
    Inventors: Paul Murtagh, Gopal Raghavan
  • Patent number: 10666268
    Abstract: Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 26, 2020
    Assignee: Eta Compute, Inc.
    Inventor: Gopal Raghavan
  • Publication number: 20200052704
    Abstract: Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 13, 2020
    Inventor: Gopal Raghavan
  • Publication number: 20190325862
    Abstract: Continuous automatic speech segmentation and recognition systems and methods are described that include a detector coupled to a neural network. The neural network performs speech recognition processing on feature vectors sequentially extracted from an audio data stream to attempt to recognize a word from a set of words of a predetermined vocabulary. The neural network has word neural paths to each output a respective word output signal to the detector for each of the set of words. The neural network also has a trigger neural path to output a trigger signal to the detector to control when the detector reviews the word output signals to recognize the word.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 24, 2019
    Inventors: Hari Shankar, Narayan Srinivasa, Gopal Raghavan, Chao Xu
  • Publication number: 20190196564
    Abstract: There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.
    Type: Application
    Filed: December 27, 2018
    Publication date: June 27, 2019
    Inventors: Paul Murtagh, Gopal Raghavan
  • Publication number: 20190190520
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 20, 2019
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
  • Patent number: 10248187
    Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device includes an asynchronous processor operative from an operating voltage and a voltage regulator circuit. The asynchronous processor includes a collection of asynchronous logic circuits that are collectively capable of executing stored instructions. The voltage regulator circuit receives a voltage request from the asynchronous processor and outputs the operating voltage to the asynchronous processor as defined by the voltage request.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 2, 2019
    Assignee: Eta Compute, Inc.
    Inventor: Gopal Raghavan
  • Patent number: 10205453
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 12, 2019
    Assignee: Eta Compute, Inc.
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
  • Publication number: 20180294810
    Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 11, 2018
    Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
  • Publication number: 20160328011
    Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device includes an asynchronous processor operative from an operating voltage and a voltage regulator circuit. The asynchronous processor includes a collection of asynchronous logic circuits that are collectively capable of executing stored instructions. The voltage regulator circuit receives a voltage request from the asynchronous processor and outputs the operating voltage to the asynchronous processor as defined by the voltage request.
    Type: Application
    Filed: July 14, 2016
    Publication date: November 10, 2016
    Inventor: Gopal Raghavan
  • Patent number: 9423866
    Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device may include an asynchronous processor and a voltage regulator circuit that outputs an operating voltage to the asynchronous processor in response to a voltage request received from the asynchronous processor.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: August 23, 2016
    Assignee: Eta Compute, Inc.
    Inventor: Gopal Raghavan
  • Publication number: 20160018869
    Abstract: There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device may include an asynchronous processor and a voltage regulator circuit that outputs an operating voltage to the asynchronous processor in response to a voltage request received from the asynchronous processor.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 21, 2016
    Inventor: Gopal Raghavan
  • Publication number: 20140355327
    Abstract: A memory system includes a controller, a first memory module, and a second memory module. The first memory module includes a first number of memory packages and a second number of memory packages. The second memory module includes a third number of memory packages and a fourth number of memory packages. The first and third numbers of memory packages are selected to correspond to a same rank based on control signals from the controller. The control signals are transmitted from the controller to the first and second memory modules through respective ones of a plurality of optical channels.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Il BYUN, Gopal RAGHAVAN, In Sung JOE
  • Patent number: 8898368
    Abstract: A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 25, 2014
    Assignee: Inphi Corporation
    Inventors: Christopher Haywood, Gopal Raghavan
  • Patent number: 8275936
    Abstract: A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: September 25, 2012
    Assignee: Inphi Corporation
    Inventors: Christopher Haywood, Gopal Raghavan, Chao Xu
  • Publication number: 20090119451
    Abstract: A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 7, 2009
    Inventors: Christopher Haywood, Gopal Raghavan
  • Patent number: 7479799
    Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: January 20, 2009
    Assignee: Inphi Corporation
    Inventors: Gopal Raghavan, Dhruv Jain
  • Patent number: 7408393
    Abstract: A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: August 5, 2008
    Assignee: Inphi Corporation
    Inventors: Dhruv Jain, Gopal Raghavan, Jeffrey C. Yen, Carl W. Pobanz
  • Patent number: 7307863
    Abstract: A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: December 11, 2007
    Assignee: Inphi Corporation
    Inventors: Jeffrey C. Yen, Nikhil K. Srivastava, Gopal Raghavan
  • Publication number: 20070216445
    Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.
    Type: Application
    Filed: March 14, 2006
    Publication date: September 20, 2007
    Inventors: Gopal Raghavan, Dhruv Jain