Patents by Inventor Gopinath Bhimarasetti

Gopinath Bhimarasetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806095
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Patent number: 9741721
    Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Joodong Park, Gopinath Bhimarasetti, Rahul Ramaswamy, Chia-Hong Jan, Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai
  • Publication number: 20170162693
    Abstract: Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion.
    Type: Application
    Filed: August 5, 2014
    Publication date: June 8, 2017
    Applicant: INTEL CORPORATION
    Inventors: Gopinath Bhimarasetti, Walid Hafez, Joodong Park, Weimin Han, Raymond Cotner
  • Publication number: 20170069725
    Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
    Type: Application
    Filed: June 26, 2014
    Publication date: March 9, 2017
    Inventors: GOPINATH BHIMARASETTI, WALID M. HAFEZ, JOODONG PARK, WEIMIN HAN, RAYMOND E. COTNER, CHIA-HONG JAN
  • Patent number: 9570467
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Publication number: 20160197082
    Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.
    Type: Application
    Filed: September 27, 2013
    Publication date: July 7, 2016
    Applicant: Intel Corporation
    Inventors: JOODONG PARK, GOPINATH BHIMARASETTI, RAHUL RAMASWAMY, CHIA-HONG JAN, WALID M. HAFEZ, JENG-YA D. YEH, CURTIS TSAI
  • Publication number: 20160111449
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 21, 2016
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Publication number: 20150179525
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Patent number: 8981481
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Publication number: 20140175566
    Abstract: A dielectric constant of spacer material in a transistor is changed from a high-? dielectric material to a low-? dielectric material. The process uses oxidation treatments to enable the transformation of the high-? dielectric material to a low-? dielectric material.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Gopinath Bhimarasetti, Walid M. Hafez, Weimin C. Han
  • Publication number: 20140001569
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Publication number: 20130313513
    Abstract: Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
    Type: Application
    Filed: December 23, 2011
    Publication date: November 28, 2013
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Gopinath Bhimarasetti, Tahir Ghani, Seiyon Kim
  • Patent number: 7597941
    Abstract: A method of synthesizing and controlling the internal diameters, conical angles, and morphology of tubular carbon nano/micro structures. Different morphologies can be synthesized included but not limited to cones, straight tubes, nozzles, cone-on-tube (funnels), tube-on-cone, cone-tube-cone, n-staged structures, multijunctioned tubes, Y-junctions, dumbbell (pinched morphology) and capsules. The process is based on changing the wetting behavior of a low melting metals such as gallium, indium, and aluminum with carbon using a growth environment of different gas phase chemistries. The described carbon tubular morphologies can be synthesized using any kind of gas phase excitation such as, but not limited to, microwave excitation, hot filament excitation, thermal excitation and Radio Frequency (RF) excitations. The depositions area is only limited by the substrate area in the equipment used and not limited by the process.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: October 6, 2009
    Assignee: University of Louisville Research Foundation, Inc.
    Inventors: Mahendra Kumar Sunkara, Gopinath Bhimarasetti
  • Publication number: 20050238567
    Abstract: A method of synthesizing and controlling the internal diameters, conical angles, and morphology of tubular carbon nano/micro structures. Different morphologies can be synthesized included but not limited to cones, straight tubes, nozzles, cone-on-tube (funnels), tube-on-cone, cone-tube-cone, n-staged structures, multijunctioned tubes, Y-junctions, dumbbell (pinched morphology) and capsules. The process is based on changing the wetting behavior of a low melting metals such as gallium, indium, and aluminum with carbon using a growth environment of different gas phase chemistries. The described carbon tubular morphologies can be synthesized using any kind of gas phase excitation such as, but not limited to, microwave excitation, hot filament excitation, thermal excitation and Radio Frequency (RF) excitations. The depositions area is only limited by the substrate area in the equipment used and not limited by the process.
    Type: Application
    Filed: September 9, 2004
    Publication date: October 27, 2005
    Inventors: Mahendra Sunkara, Gopinath Bhimarasetti