Abstract: The present application at least describes an apparatus for managing traffic. The apparatus includes a display including a graphical user interface. The apparatus also includes a non-transitory memory including information for managing traffic and a processor operably coupled to the display and memory, and configured to execute an instruction of receiving, via the graphical user interface, a request from a buyer to purchase a right of way from an entity at a traffic location. Another instruction includes reviewing, via gps, a location or route of the buyer in relation to the traffic location. Yet another instruction includes reviewing, via gps, a location or route of the entity in relation to the traffic location. Yet even another instruction includes determining, based upon the reviewed locations of the buyer and the entity, whether to send the buyer request to the entity; and sending, based upon the determination, the request to the entity.

Abstract: Aspects herein relate to storing information concerning rights and liabilities or other records on distributed ledgers. A method disclosed can include identifying a transferor blockchain associated with rights and liabilities for transfer from a transferor to an acquirer, identifying an acquirer blockchain associated with the acquirer, creating an interim blockchain including the rights and liabilities, generating entries to the transferor blockchain removing the rights and liabilities, and generating entries to the acquirer blockchain adding the rights and liabilities. Another method disclosed can include identifying a critical record of a party, identifying a blockchain associated with the party, and generating an entry on the blockchain associated with the critical record, the entry having permissions related to at least the party.

Abstract: The application is directed to a computer-implemented apparatus for facilitating transactions. The apparatus includes a non-transitory memory having instructions stored thereon for performing an evaluation of user performance prior to proceeding with a transaction. The apparatus also includes a processor, operably coupled to the non-transitory memory. The processor is configured to perform the instructions of displaying, on a graphical user interface (GUI), an input box requesting a user to input information associated with the transaction. The processor is also configured to receive, via the GUI, information from the user associated with the transaction. The processor is also configured to perform the instruction of evaluating the received information associated with the transaction based upon decision criteria.

Abstract: Aspects herein relate to storing information concerning rights and liabilities or other records on distributed ledgers. A method disclosed can include identifying a transferor blockchain associated with rights and liabilities for transfer from a transferor to an acquirer, identifying an acquirer blockchain associated with the acquirer, creating an interim blockchain including the rights and liabilities, generating entries to the transferor blockchain removing the rights and liabilities, and generating entries to the acquirer blockchain adding the rights and liabilities. Another method disclosed can include identifying a critical record of a party, identifying a blockchain associated with the party, and generating an entry on the blockchain associated with the critical record, the entry having permissions related to at least the party.

Abstract: The application is directed to a computer-implemented apparatus for facilitating transactions. The apparatus includes a non-transitory memory having instructions stored thereon for performing an evaluation of user performance prior to proceeding with a transaction. The apparatus also includes a processor, operably coupled to the non-transitory memory. The processor is configured to perform the instructions of displaying, on a graphical user interface (GUI), an input box requesting a user to input information associated with the transaction. The processor is also configured to receive, via the GUI, information from the user associated with the transaction. The processor is also configured to perform the instruction of evaluating the received information associated with the transaction based upon decision criteria.

Abstract: The present application at least describes an apparatus for managing traffic. The apparatus includes a display including a graphical user interface. The apparatus also includes a non-transitory memory including information for managing traffic and a processor operably coupled to the display and memory, and configured to execute an instruction of receiving, via the graphical user interface, a request from a buyer to purchase a right of way from an entity at a traffic location. Another instruction includes reviewing, via gps, a location or route of the buyer in relation to the traffic location. Yet another instruction includes reviewing, via gps, a location or route of the entity in relation to the traffic location. Yet even another instruction includes determining, based upon the reviewed locations of the buyer and the entity, whether to send the buyer request to the entity; and sending, based upon the determination, the request to the entity.

Abstract: Aspects herein relate to storing information concerning rights and liabilities or other records on distributed ledgers. A method disclosed can include identifying a transferor blockchain associated with rights and liabilities for transfer from a transferor to an acquirer, identifying an acquirer blockchain associated with the acquirer, creating an interim blockchain including the rights and liabilities, generating entries to the transferor blockchain removing the rights and liabilities, and generating entries to the acquirer blockchain adding the rights and liabilities. Another method disclosed can include identifying a critical record of a party, identifying a blockchain associated with the party, and generating an entry on the blockchain associated with the critical record, the entry having permissions related to at least the party.

Abstract: Techniques are described for managing a transaction, such as a purchase of a vehicle or other product, using one or more blockchains. The completion of a transaction may be facilitated by providing an information portal, such as one or more application user interfaces, to enable the buyer, seller, or other parties to readily access blockchain-stored information that is relevant to the transaction. In some examples, where the product to be purchased is a vehicle (e.g., car, truck, motorcycle, boat, etc.), the blockchain-stored information may include information regarding the loan, title, insurance, driver's license or other identification verification, vehicle ownership history, inspection history, repair history, lien information, and so forth. The portal also enables a point of contact to be maintained between the buyer and a lender during the process of purchasing the product.

Abstract: To achieve an even distribution of different types of connections, sets of connection cells have been devised having different ratios of signal, power and ground connections in which the signal connections are all within a maximum distance of a power and/or a ground connection. In addition, the shapes of the cells are such that the cells fit together in a repeatable array that fully covers the plane of the interface, i.e., an array that tiles the plane. Accordingly, to distribute the connections substantially uniformly across the interface, the ratio of the number of signal connections, power connections and ground connections is determined; a cell is selected from the set of cells that has approximately the same ratio of the number of signal connections, power connections and ground connections; and the selected cell is repeatedly used to allocate the signal, power and ground connections in accordance with the distribution of connections in the selected cell until all the connections are distributed.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.

Abstract: Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

Abstract: Circuits, methods, and apparatus for protecting devices in an output stage from over-voltage conditions caused by high supply and input voltages. Embodiments provide over-voltage protection that operates over a range of voltage levels, and that can be optimized for performance at different voltage levels. An exemplary embodiment of the present invention uses stacked devices to protect n and p-channel output devices from excess supply and input voltages. These stacked devices are biased by voltages received at their gates. These gate voltages vary as a function of supply voltage to maintain performance. Other embodiments of the present invention provide a body bias switch that generates a bias for the bulk of p-channel output devices. This bias tracks the higher of a supply or input voltage, such that parasitic drain-to-bulk diodes do not conduct. A switch may be provided that shorts the bulk connection to VCC under appropriate conditions.

Abstract: A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

Abstract: A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.