Patents by Inventor Gordon Raymond Chiu

Gordon Raymond Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10726328
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes identifying characteristics and parameters for the CNN accelerator. Resources on the target are identified. A design for the CNN accelerator is generated in response to the characteristics and parameters of the CNN accelerator and the resources on the target.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 28, 2020
    Assignee: Altera Corporation
    Inventors: Andrew Chaang Ling, Gordon Raymond Chiu, Utku Aydonat
  • Publication number: 20200193267
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Inventors: Utku Aydonat, Gordon Raymond Chiu, Andrew Chaang Ling
  • Patent number: 10671781
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa, David Ian M. Milton
  • Patent number: 10614354
    Abstract: A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.
    Type: Grant
    Filed: February 6, 2016
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventors: Utku Aydonat, Gordon Raymond Chiu, Andrew Chaang Ling
  • Publication number: 20200050729
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 13, 2020
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Patent number: 10394997
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 27, 2019
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Patent number: 10387603
    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 20, 2019
    Assignee: Altera Corporation
    Inventors: Nishanth Sinnadurai, Gordon Raymond Chiu
  • Patent number: 10339238
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: July 2, 2019
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa
  • Patent number: 10339244
    Abstract: A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 2, 2019
    Assignee: Altera Corporation
    Inventors: Benjamin Gamsa, Gordon Raymond Chiu
  • Patent number: 10224908
    Abstract: An integrated circuit may include path delay calibration circuitry. The calibration circuitry may be configured to calibrate respective delay paths so that data and control signals travelling through the respective delay paths experience proper propagation delays during normal user operation. The calibration circuitry may include a high frequency error calibration circuit, a monitoring circuit, and a calibration processing circuit. The high frequency error calibration circuit may be used to compute first calibration settings that take into account jitter and process variations. The monitoring circuit may be used to measure a proxy parameter of interest. The processing circuit may be used to compute an offset based at least partly on the measured value of the proxy parameter. The offset may be applied to the first calibration settings to obtain second calibration settings, which can be used to configure the respective delay paths.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 5, 2019
    Assignee: Altera Corporation
    Inventors: Joshua David Fender, Navid Azizi, Gordon Raymond Chiu
  • Publication number: 20190065652
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Application
    Filed: September 18, 2018
    Publication date: February 28, 2019
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Patent number: 10157250
    Abstract: In one embodiment, a tangible, non-transitory, computer-readable medium, includes instructions to receive a first circuit design, determine one or more variations of the first circuit design using register retiming with speculative circuit design changes, determine one or more performance improvements of the variations when fed clock signals over the first circuit design, determine one or more tradeoffs of the one or more variations of the first circuit design in comparison to the first circuit design, display a summary of the one or more variations of the first circuit design, the one or more performance improvements, and the one or more tradeoffs, and provide a user-selectable user interface element to enable selection of the first circuit design, at least one of the one or more variations of the first circuit design, or a combination thereof.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 18, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Benjamin Michael Joshua Gamsa, Gordon Raymond Chiu
  • Patent number: 10152565
    Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: December 11, 2018
    Assignee: Altera Corporation
    Inventors: Benjamin Gamsa, Gordon Raymond Chiu
  • Patent number: 10102326
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 16, 2018
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Publication number: 20180293343
    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 11, 2018
    Inventors: Nishanth Sinnadurai, Gordon Raymond Chiu
  • Patent number: 10083007
    Abstract: Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. Intermediate filter values are calculated from filter elements of the filter using the transformation function. Each intermediate input value is multiplied with a respective intermediate filter value to form intermediate values. These intermediate values are combined with each other using the transformation function to determine one or more output values.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 25, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Utku Aydonat, Andrew Chaang Ling, Gordon Raymond Chiu, Shane O'Connell
  • Publication number: 20180232475
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Salem DERISAVI, Gordon Raymond CHIU, Benjamin GAMSA, David Ian M. MILTON
  • Patent number: 9996652
    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 12, 2018
    Assignee: Altera Corporation
    Inventors: Nishanth Sinnadurai, Gordon Raymond Chiu
  • Patent number: 9971858
    Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: May 15, 2018
    Assignee: Altera Corporation
    Inventors: Salem Derisavi, Gordon Raymond Chiu, Benjamin Gamsa, David Ian M. Milton
  • Patent number: 9948307
    Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 17, 2018
    Assignee: ALTERA CORPORATION
    Inventors: Navid Azizi, Gordon Raymond Chiu, Michael Howard Kipper