Abstract: A circuit design may have registers and combinational gates. Circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across combinational gates. Information about the register moves may be recorded, and a modified circuit design is created. The circuit design computing equipment may implement the circuit design in an integrated circuit. A logic analyzer may be used to debug the circuit design implemented in the integrated circuit in real-time and at high-speed. To facilitate the debugging process, the circuit design computing equipment may augment the integrated circuit and/or compensate for register retiming based on the information recorded during register retiming.

Abstract: Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

Abstract: A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Abstract: A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

Abstract: A method of configuring an integrated circuit device with a user logic design includes placing and routing the user logic design, retiming the placed and routed user logic design, examining the retimed user logic design for at least one path that lacks sufficient registers for retiming, and rerouting the user logic design to find additional registers for further retiming the at least one path. Portions of the method may be performed iteratively until a condition, which may be a performance criterion, is met. The method may further include assuming the paths that are constrained have been repaired, and examining further paths downstream from those paths.

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract: An integrated circuit such as a programmable integrated circuit may include input-output circuits each having respective memory controller circuitry. The memory controller circuitry of the input-output circuits may be electrically coupled via a backbone path and configured to collectively form a memory controller. Each memory controller circuitry may include a protocol control circuit and input-output lanes. Memory access requests from on-chip circuitry may be provided to only a selected input-output circuit. The protocol control circuit of the selected input-output circuit may receive the memory access requests and generate memory control signals and local control signals from the memory access requests. The memory control signals may be provided to external memory. The local control signals may be provided to input-output circuits over the backbone path and synchronize the input-output circuits in conveying data between the integrated circuit and the external memory.

Abstract: Integrated circuits such as programmable integrated circuits may include calibration circuitry for calibrating memory interface circuitry. The calibration circuitry may include processing circuitry and test circuitry. The processing circuitry may provide instructions to the test circuitry and direct the test circuitry to begin processing at a selected instruction. The test circuitry may retrieve data storage addresses and control signal storage addresses from the instructions. The test circuitry may use the data storage address to retrieve test data from data storage circuitry and may use the control signal storage address to retrieve control signal data from control signal storage circuitry. The control signal, address, and test data may be provided to the memory interface circuitry. The test circuitry may verify data received from the system memory during instruction processing.

Abstract: A method for designing a system on a target device includes performing register retiming on the system. A critical chain in the system is detected, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths. The system is modified in response to properties of the critical chain.

Abstract: A method for designing a system on a target device includes performing register retiming on the system. A critical chain in the system is detected, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths. Properties of the critical chain are reported.

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract: Architecture, systems, and methods for developing, an area-efficient dynamically-configurable memory controller are described. The architecture, systems and methods may provide savings in terms of surface area required for implementing a dynamically configurable hardened memory controller or controllers.

Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.

Abstract: Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.

Abstract: Techniques and mechanisms allow a device such as a programmable logic device (PLD) to support real-time debugging of a system. The PLD may be configured to include a debug design without disturbing the configuration of a base logic design in the PLD.

Abstract: Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.

Abstract: A method for using computing equipment to perform timing analysis on an integrated circuit design includes identifying a timing arc of the integrated circuit design. The timing arc may be a clock path or a data path in the integrated circuit design. A probability of the timing arc may be obtained and an aging effect for the timing arc may be calculated. The aging effect of the timing arc is calculated based on the probability. The timing arc may include maximum and minimum delays that are adjusted based at least partly on the calculated aging effect on the timing arc.

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract: In a memory interface circuit (e.g., a programmable logic device), a clock or strobe (DQS) signal can be gated using a clock-like signal that can also be used to sample the DQS signal. Furthermore, both the rising and falling edges of the DQS signal can be sampled using the clock-like signal.