Abstract: Disclosed herein is a device that includes first and second spaced-apart conductive pads positioned in a layer of insulating material, first and second under-bump metallization layers that are conductively coupled to the first and second conductive pads, respectively, and first and second spaced-apart conductive bumps that are conductively coupled to the first and second under-bump metallization layers, respectively. Additionally, the device includes, among other things, a passivation layer positioned above the layer of insulating material between the first and second spaced-apart conductive bumps, and a protective layer positioned on the passivation layer, wherein the protective layer extends between and contacts the first and second under-bump metallization layers, the material of the protective layer being one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN).

Abstract: One illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad, forming a protective layer on the passivation layer, in the opening and on the exposed portion of the conductive pad, forming a heat-curable material layer above the protective layer, performing an etching process to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process on the protective layer to thereby expose at least a portion of the conductive pad and forming a conductive bump that is conductively coupled to the conductive pad.

Abstract: One illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad, forming a protective layer on the passivation layer, in the opening and on the exposed portion of the conductive pad, forming a heat-curable material layer above the protective layer, performing an etching process to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process on the protective layer to thereby expose at least a portion of the conductive pad and forming a conductive bump that is conductively coupled to the conductive pad.

Abstract: In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold.

Abstract: Solder balls of semiconductor devices and, in particular, lead-free solder balls receive a very uniform passivation layer, for instance in the form of an oxide layer, which is formed by applying a plasma treatment. For example, the passivation layer may be provided with a thickness of 5-50 nm which may thus allow, due to the superior uniformity, a reliable protection of the solder balls while nevertheless ensuring a reliable removal during the final solder process.

Abstract: In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold.

Abstract: By controlling the cooling rate during the oxidation process for forming an oxide layer on solder balls and by selecting an elevated temperature as an initial temperature of the oxidation process, a reliable yet easily removable oxide layer may be obtained. Consequently, yield losses during the flip chip assembly process may be significantly reduced.

Abstract: By patterning the underbump metallization layer stack on the basis of a dry etch process, significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer of an underbump metallization layer stack may be etched on the basis of a plasma etch process using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes may be performed for removing particles and residues prior to and after the plasma-based patterning process.

Abstract: By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may significantly be reduced.

Abstract: The present invention provides a new technology approach for forming a contact layer in a microelectronic chip, which includes a plurality of solder bumps that are directly to be connected with a correspondingly designed carrier substrate. In the process flow, a plasma-based process for patterning the underbump metallization layer is used in combination with testing and assembling the device, thereby providing a high degree of process flexibility and/or cost reduction and/or device performance.

Abstract: A method of forming backside metallization on a substrate that includes a plurality of integrated circuit die formed on a front side of the substrate is disclosed. The method includes forming an adhesion layer of aluminum or an aluminum alloy on a backside surface of the substrate, forming a barrier metal layer on the adhesion layer and forming a metal layer on the barrier metal layer. An integrated circuit device is also disclosed which includes a substrate having an integrated circuit die formed on a front side of the substrate, an adhesion layer on a backside surface of the substrate, wherein the adhesion layer is aluminum or an aluminum alloy, a barrier metal layer on the adhesion layer and a metal layer on the barrier metal layer.

Abstract: By directly forming an underbump metallization layer on a contact region of the last metallization layer, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers, may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may be significantly reduced.

Abstract: By controlling the cooling rate during the oxidation process for forming an oxide layer on solder balls and by selecting an elevated temperature as an initial temperature of the oxidation process, a reliable yet easily removable oxide layer may be obtained. Consequently, yield losses during the flip chip assembly process may be significantly reduced.

Abstract: By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may significantly be reduced.

Abstract: By patterning the underbump metallization layer stack on the basis of a dry etch process, significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer of an underbump metallization layer stack may be etched on the basis of a plasma etch process using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes may be performed for removing particles and residues prior to and after the plasma-based patterning process.

Abstract: The present invention provides a new technology approach for forming a contact layer in a microelectronic chip, which includes a plurality of solder bumps that are directly to be connected with a correspondingly designed carrier substrate. In the process flow, a plasma-based process for patterning the underbump metallization layer is used in combination with testing and assembling the device, thereby providing a high degree of process flexibility and/or cost reduction and/or device performance.

Abstract: A method comprises a “two-step” formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.

Abstract: A method comprises a “two-step” formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.