INTEGRATED CIRCUIT DEVICES WITH BUMP STRUCTURES THAT INCLUDE A PROTECTION LAYER
Disclosed herein is a device that includes first and second spaced-apart conductive pads positioned in a layer of insulating material, first and second under-bump metallization layers that are conductively coupled to the first and second conductive pads, respectively, and first and second spaced-apart conductive bumps that are conductively coupled to the first and second under-bump metallization layers, respectively. Additionally, the device includes, among other things, a passivation layer positioned above the layer of insulating material between the first and second spaced-apart conductive bumps, and a protective layer positioned on the passivation layer, wherein the protective layer extends between and contacts the first and second under-bump metallization layers, the material of the protective layer being one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN).
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1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive bump structures on integrated circuit devices and devices comprising such structures.
2. Description of the Related Art
In the manufacture of modern integrated circuits, it is usually necessary to provide electrical connections between the various semiconductor chips making up a microelectronic device. Depending on the type of chip and the overall device design requirements, these electrical connections may be accomplished in a variety of ways, such as, for example, by wire bonding, tape automated bonding (TAB), flip-chip bonding, and the like. In recent years, the use of flip-chip technology, wherein semiconductor chips are attached to substrates, carriers, or other chips by means of solder balls formed from so-called solder bumps, has become an important aspect of the semiconductor processing industry. In flip-chip technology, solders balls are formed on a contact layer of at least one of the chips that is to be connected, such as, for example, on a dielectric passivation layer formed above the last metallization layer of a semiconductor chip comprising a plurality of integrated circuits. Similarly, adequately sized and appropriately located bond pads are formed on another chip, such as, for example, a carrier package, each of which corresponds to a respective solder ball formed on the semiconductor chip. The two units, i.e., the semiconductor chip and carrier package, are then electrically connected by “flipping” the semiconductor chip and bringing the solder balls into physical contact with the bond pads, and performing a “reflow” process so that each solder ball bonds to a corresponding bond pad. Typically, hundreds, or even thousands, of solder bumps may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern semiconductor chips that usually include complex circuitry, such as microprocessors, storage circuits, three-dimensional (3D) chips, and the like, and/or a plurality of integrated circuits forming a complete complex circuit system.
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The present disclosure is directed to various methods of forming conductive bumps on a semiconductor device that may at least reduce or eliminate one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming conductive bump structures on integrated circuit devices, wherein, in some embodiments, a protective layer is employed, and devices comprising such structures. In one example, the method includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad and the layer of insulating material, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad and forming a protective layer on the passivation layer, in the opening and on the exposed portion of said conductive pad. In this example the method further includes the steps of forming a heat-curable material layer (such as a polyimide layer or a PBO layer) above the protective layer, performing an etching process on the heat-curable material layer to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process to remove the exposed portion of the protective layer to thereby expose at least a portion of the conductive pad and, after removing the exposed portion of the protective layer, forming a conductive bump that is conductively coupled to the conductive pad.
In one illustrative embodiment, a device disclosed herein includes first and second spaced-apart conductive pads positioned in a layer of insulating material, first and second under-bump metallization layers that are conductively coupled to the first and second conductive pads, respectively, and first and second spaced-apart conductive bumps, each of which are conductively coupled to the first and second under-bump metallization layers, respectively. In this example, the device further includes a passivation layer positioned above the layer of insulating material between the first and second spaced-apart conductive bumps and a protective layer positioned on the layer of insulating material, wherein the protective layer extends between and contacts the first and second under-bump metallization layers.
Another illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a multi-layer passivation layer above the conductive pad and above the layer of insulating material, wherein a first layer of the multi-layer passivation layer is in contact with the conductive pad and the layer of insulating material, performing at least one etching process on the multi-layer passivation layer to remove at least one layer of the multi-layer passivation layer, to thereby define an etched passivation layer having a recess that exposes at least a portion of the first layer and forming a heat-curable material layer above the etched passivation layer and the exposed portion of said first layer. In this example, the method further includes performing an etching process on the heat-curable material layer to define a patterned heat-curable material layer having an opening that exposes a portion of the etched passivation layer and the exposed portion of the first layer, performing an etching process to remove the exposed portion of the first layer to thereby expose at least a portion of the conductive pad and after removing the exposed portion of the first layer, forming a conductive bump that is conductively coupled to the conductive pad.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming conductive bump structures on integrated circuit devices. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein are applicable to a variety of devices, including, but not limited to, ASICs, logic devices, memory devices, etc. With reference to
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The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1.-25. (canceled)
26. A device, comprising:
- first and second spaced-apart conductive pads positioned in a layer of insulating material;
- first and second under-bump metallization layers that are conductively coupled to said first and second conductive pads, respectively;
- first and second spaced-apart conductive bumps that are conductively coupled to said first and second under-bump metallization layers, respectively;
- a passivation layer positioned above said layer of insulating material between said first and second spaced-apart conductive bumps; and
- a protective layer positioned on said passivation layer, wherein said protective layer extends between and contacts said first and second under-bump metallization layers and comprises one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN).
27. The device of claim 26, wherein a portion of said passivation layer extends over and contacts a portion of each of said first and second contact pads, said passivation layer being positioned between said first and second under-bump metallization layers and said respective portions of said first and second contact pads.
28. The device of claim 26, wherein said protective layer has a thickness in the range of approximately 20-300 nm.
29. The device of claim 26, wherein each of said first and second gate spaced-apart conductive bumps comprise tin and at least one of silver and copper.
30. The device of claim 29, wherein each of said first and second spaced-apart conductive pads comprise copper.
31. The device of claim 26, wherein said passivation layer is a multi-layer passivation layer, said multi-layer passivation layer comprising:
- a first layer comprised of silicon, carbon, and nitrogen, wherein said first layer is positioned on said layer of insulating material and extends over and contacts a portion of each of said first and second contact pads;
- a second layer comprised of silicon dioxide positioned on said first layer; and
- a third layer comprised of silicon nitride positioned on said second layer.
32. The device of claim 31, wherein said protective layer is positioned on said third layer.
33. The device of claim 26, further comprising a heat-cured material layer positioned on said protective layer, said heat-cured material layer extending between and contacting said first and second under-bump metallization layers.
34. The device of claim 33, wherein said heat-cured material layer comprises one of polyimide and polybenzoxadiaziole (PBO).
35. A device, comprising:
- first and second spaced-apart conductive pads positioned in a layer of insulating material;
- a first under-bump metallization layer conductively coupled to said first conductive pad;
- a second under-bump metallization layer conductively coupled to said second conductive pad;
- first and second spaced-apart conductive bumps that are conductively coupled to said respective first and second under-bump metallization layers;
- a multi-layer passivation layer positioned above said layer of insulating material, said multi-layer passivation layer extending between and contacting each of said first and second under-bump metallization layers, wherein a bottom layer of said multi-layer passivation layer extends over and contacts portions of said first and second contact pads; and
- a protective layer positioned on said top layer of said multi-layer passivation layer, said protective layer extending between and contacting each of said first and second under-bump metallization layers.
36. The device of claim 35, wherein said protective layer comprises one of silicon dioxide, silicon oxyfluoride (SiOF), silicon nitride (SiN), and silicone carbon nitride (SiCN).
37. The device of claim 36, wherein a thickness of said protective layer is in the range of approximately 20-300 nm.
38. The device of claim 35, wherein said top layer of said multi-layer passivation layer comprises silicon nitride and said bottom layer of said multi-layer passivation layer comprises silicon, carbon, and nitrogen.
39. The device of claim 35, wherein said multi-layer passivation layer comprises an intermediate layer positioned between said top and layer said bottom layer, said intermediate layer comprising silicon dioxide.
40. The device of claim 35, wherein each of said first and second gate spaced-apart conductive bumps comprise tin and at least one of silver and copper.
41. The device of claim 35, wherein each of said first and second spaced-apart conductive pads comprise copper.
42. The device of claim 35, further comprising a heat-cured material layer positioned on said protective layer, said heat-cured material layer extending between and contacting said first and second under-bump metallization layers.
43. The device of claim 42, wherein said heat-cured material layer comprises one of polyimide and polybenzoxadiaziole (PBO).
Type: Application
Filed: Sep 27, 2013
Publication Date: Jan 23, 2014
Applicant: GLOBALFOUNDRIES Inc. (Grand Cayman)
Inventors: Frank Kuechenmeister (Dresden), Lothar Lehmann (Radebeul), Alexander Platz (Ebersbach), Gotthard Jungnickel (Radeberg), Sven Kosgalwies (Dresden)
Application Number: 14/039,726