Patents by Inventor Gowrisankar Damarla

Gowrisankar Damarla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263459
    Abstract: A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Hongqi Li, Gowrisankar Damarla, Roger Lindsay, Zailong Bian, Jin Lu, Shyam Ramalingam, Prasanna Srinivasan
  • Publication number: 20150340247
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 26, 2015
    Applicant: Sony Corporation
    Inventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
  • Publication number: 20150243583
    Abstract: A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Gowrisankar Damarla, Shyam Ramalingam
  • Publication number: 20150054164
    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Hongqi Li, Gowrisankar Damarla, Robert J. Hanson, Jin Lu, Shyam Ramalingam