Abstract: To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).

Abstract: A non volatile memory (100) includes an array (102) of transistors (30) having discrete charge storage elements (40). The transistors are programmed by using a two step programming method (60) where a first step (68) is hot carrier injection (HCI) programming with low gate voltages. A second step (78) is selectively utilized on some memory cells to modify the injected charge distribution to enhance the separation of charge distribution between each memory bit within the transistor memory cell. The second step of programming is implemented without adding significant additional time to the programming operation. In one example, the first step injects electrons and the second step injects holes. The resulting distribution of the two steps removes electron charge in the central region of the storage medium.

Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46).