Abstract: An erase of a non-volatile memory (NVM) is achieved by first using oxide tunneling followed by hot hole injection (HHI). The subsequent use of HHI completes the erase that the tunneling cannot complete due to saturation. By first using tunneling, preferably Fowler-Nordheim tunneling (FNT), the damage to a bottom dielectric that normally occurs by HHI is significantly reduced. The damage due to HHI is significantly greater at the beginning of the erase when the electric field is greater. By reducing the damage due to HHI, the bottom dielectric can be smaller than that normally used for HHI so that high voltages are not required. Accordingly, the transistors in the periphery do not need to be so oversized as is normally required for HHI and thus saving area and power.

Abstract: A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the memory device (70) uses a counterdoped channel (86) to lower the natural threshold voltage of the device (70). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel (86) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region (74) below the channel (86) allows for the lightly doped or reversed conductivity type channel (86) to avoid short channel leakage. A halo implant (46) on the drain side (54, 53) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel (86) is lightly doped or of reversed conductivity type.

Abstract: A non-volatile multiple bit memory (10, 50) has electrically isolated storage elements (17, 21, 78, 80) that overlie a channel region having a central area (24, 94) with high impurity concentration. A planar gate (30, 84) overlies the storage elements. The high impurity concentration may be formed by a centrally located region (24) or by two peripheral regions (70, 72) having lower impurity concentration than the central portion of the channel. During a read or program operation, the channel area of high impurity concentration effectively controls a channel depletion region to enhance reading or programming of stored data bits. During a hot carrier program operation, the channel area of high impurity concentration enhances the programming efficiency by decreasing leakage currents in a memory array.

Abstract: In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate (12) by forming elevated sources and drains (56) in contact with extensions (46) within the top silicon layer (18) of the SOI substrate (12). Buried conductive regions (42) are formed within the top silicon layer (18) below the extensions (46) to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (56), extensions (46) and the buried conductive regions (42) in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (56), extensions (46) and the buried conductive regions (42).

Abstract: A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.