Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: In general, embodiments of the technology relate to a method for managing data. The method includes, in response to initiating garbage collection on a storage appliance, selecting a first block from the plurality of blocks based, at least in part, on a selection frequency; and performing a garbage collection operation on the first block to generate a first erased block in the storage appliance.

Abstract: In general, embodiments of the technology relate to a method for storing data. More specifically, the method may include selecting a first RAID grid location in a RAID grid, where the first RAID grid location is flagged, selecting a second RAID grid location in the RAID grid, making a first determination that the second RAID grid location is not flagged, in response to the first determination, loading first data associated with the second RAID grid location into a cache, calculating a parity value for a corresponding set of RAID grid locations in a data grid using the first data in the cache, where the first RAID grid location and the second RAID grid location are in the set of RAID grid locations, and storing at least a copy of the first data and the parity value in a storage array comprising persistent storage.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Abstract: Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Abstract: The present invention provides a hydrocolloid composition which, based on 100% by weight of the hydrocolloid composition, comprises: 10-90%) by weight of a polyisobutylene tackifier; 5-55% by weight of a hydrophilic absorbing substance; and 0.1-20% by weight of a functional ingredient. The invention further provides an article containing the hydrocolloid composition.

Abstract: Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Abstract: Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Abstract: In a processing system which includes a physical processor that includes multiple logical processors, multiple domains are defined for multiple processes that can execute on the physical processor. Each of the processes is assigned to one of the domains. Processor utilization associated with the logical processors is measured, and each of the domains is allocated to a subset of the logical processors according to the processor utilization.

Abstract: Embodiments of the invention may improve read operations for fully cached workloads on storage systems with limited processing or CPU-cache resources. Some embodiments employ an indicator such as a counter to indicate when the use of readahead analysis steps, such as resource, intensive predictive processing, is undesirable. In these embodiments, the counter is incremented for each buffer cache read that is successfully performed without the need for a disk input/output operation. When the counter variable exceeds a threshold such as, for example, a maximum readahead size, then the system advantageously foregoes predictive processing steps of the readahead analysis phase, and further foregoes a readahead execution phase. The foregoing results in a net performance benefit for the system based on a reduced likelihood of a need for an input/output operation, and further, based on a reduced likelihood of a need for predictive processing relating to readahead analysis and/or execution.

Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.

Abstract: In a processing system which includes a physical processor that includes multiple logical processors, multiple domains are defined for multiple processes that can execute on the physical processor. Each of the processes is assigned to one of the domains. Processor utilization associated with the logical processors is measured, and each of the domains is allocated to a subset of the logical processors according to the processor utilization.