Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items.

Abstract: An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.

Abstract: A nonlinear crystal comprising a first curved face and an opposing second curved face is described. The first and second curved faces are arranged to provide the nonlinear crystal with rotational symmetry about at least one axis of the nonlinear crystal. The nonlinear crystal allows for frequency tuning of a generated optical field that is generated by propagating a fundamental optical field through the nonlinear crystal by rotation of the nonlinear crystal about an axis of rotation without any significant, or minimal, deviation being introduced to the generated optical field. These nonlinear crystals can therefore be incorporated into an external cavity frequency doubler or mixer without any need for the employment of optical compensation optics or servo control electronics to automatically realign the cavity mirrors.

Abstract: An apparatus and method are provided for generating signed bounded pointers from general purpose specified data, for example data that may exist within a backing store such as a disk. The apparatus has processing circuitry that is responsive to a bounded pointer generation request to perform a generation operation to generate a bounded pointer from the specified data provided at least one generation condition is met. The bounded pointer comprises a pointer value and associated attributes, and the associated attributes include range information indicative of an allowable range of addresses when using the pointer value.

Abstract: An optical frequency mixing module is described that comprises a nonlinear medium for frequency mixing the photons of one or more input optical fields to generate an output optical field; a nonlinear medium tuner for automatically phase matching the nonlinear medium to the one or more input optical fields to select the wavelength of the output optical field generated by the nonlinear medium; and a first direction correcting optic. The position of the first direction correcting optic relative to the nonlinear medium is dependent upon the selected wavelength of the output optical field and therefore ensures that the position and angle of propagation of this field remains constant and independent of its wavelength of. The optical frequency mixing modules therefore provides a means for automatically selecting the wavelength of the output field with no deviation being imparted onto the position or angle of propagation of the output field.

Abstract: An apparatus comprises address translation circuitry to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses. The stored page table mappings comprise tag-guard control information. The apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target physical address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address. The memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information.

Abstract: An apparatus has memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. An instruction decoder decodes a multiple guard tag setting instruction to control the memory access circuitry to trigger memory accesses to update the guard tags associated with at least two consecutive blocks of one or more memory locations.

Abstract: An apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address. The memory access circuitry is responsive to a sequence of received target addresses specifying a sequence of addressed locations to perform a non-tag-guarded memory access that does not perform the guard-tag check to a subset of the sequence of addressed locations.

Abstract: An apparatus and method are provided for controlling execution of certain instructions. The apparatus has processing circuitry to execute a sequence of instructions, an integer storage element to store an integer value for access by the processing circuitry, and a capability storage element for storing a capability for access by the processing circuitry. A capability usage storage is then used to store capability usage information. The processing circuitry is responsive to execution of at least one instruction in the sequence of instructions to generate, in dependence on the capability usage information, a result to be stored in a destination storage element. In particular, when the capability usage information identifies a capability state, the result is generated as a capability, and the capability storage element is selected as the destination storage element.

Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.

Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus has a plurality of bounded pointer storage elements, each bounded pointer storage element being used to store a bounded pointer and associated permission attributes indicative of allowed uses of the bounded pointer. In accordance with the present technique, the associated permission attributes include a copy permission attribute indicating whether the bounded pointer is allowed to be subjected to a copy operation. Processing circuitry is then responsive to at least one instruction that specifies the copy operation, to generate, from a source bounded pointer and associated permission attributes of a source bounded pointer storage element, a destination bounded pointer and associated permission attributes to be stored in a destination bounded pointer storage element.

Abstract: An apparatus and method are provided for interpreting permissions associated with a capability. The apparatus has processing circuitry for executing instructions in order to perform operations, and a capability storage element accessible to the processing circuitry and arranged to store a capability used to constrain at least one operation performed by the processing circuitry when executing the instructions. The capability identifies a plurality N of default permissions whose state, in accordance with a default interpretation, is determined from N permission flags provided in the capability. In accordance with the default interpretation, each permission flag is associated with one of the default permissions. The processing circuitry is then arranged to analyse the capability in accordance with an alternative interpretation, in order to derive, from logical combinations of the N permission flags, state for an enlarged set of permissions, where the enlarged set comprises at least N+1 permissions.

Abstract: An apparatus and method are provided for managing use of capabilities. The apparatus has processing circuitry to execute instructions, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing instructions. The processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege. Further, capability configuration storage is provided to identify capability configuration information for each of the plurality of exception levels. For each exception level, the capability configuration information identifies at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by capabilities.

Abstract: An electro-optic modulator (EOM) for altering an optical path length of an optical field is described. The EOM comprises first and second Brewster-angle cut nonlinear crystals having a first and second optical axis. The optical axes are orientated relative to each other such that when an optical field propagates through the nonlinear crystals it experiences no overall deviation. The nonlinear crystals are also arranged to be opposite handed relative to the optical field. The EOM has the advantage that its optical losses are lower when compared with those EOMs known in the art. In addition, the EOM can be inserted into, or removed from, an optical system without any deviation being imparted onto the optical field. This reduces the levels of skill and effort required on the part of an operator. The described method and apparatus for mounting the nonlinear crystals also suppresses problematic piezo-electric resonances within the nonlinear crystals.

Abstract: An apparatus and method are provided for controlling a change in instruction set. The apparatus has processing circuitry to execute instructions of an instruction set, with the processing circuitry being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is used to store a program counter capability used by the processing circuitry to determined a program counter value. The processing circuitry is arranged to employ a capability based mechanism to change the instruction set.

Abstract: An apparatus and method are provided for controlling instruction execution behaviour. The apparatus includes a set of data registers for storing data values, and a set of bounded pointer storage elements, where each bounded pointer storage element stores a pointer having associated range information indicative of an allowable range of addresses when using that pointer. A control storage element stores a current instruction context, and that current instruction context is used to influence the behaviour of at least one instruction executed by processing circuitry, that at least one instruction specifying a pointer reference for a required pointer, where the pointer reference is within at least a first subset of values (in one embodiment the behaviour is influenced irrespective of the value of the required pointer).

Abstract: A hollow plastic wall panel, the panel having a length greater than a width, a thickness less than the width, a front wall, an opposite back wall and opposed first and second long edge regions, wherein the panel comprises a first end and a longitudinally opposite second end, wherein the first long edge region defines at least one first recessed portion to longitudinally receive and mate with a first longitudinal support structure and wherein the second long edge region defines at least one second recessed portion to longitudinally receive and mate with a second longitudinal support structure.

Abstract: A nonlinear crystal comprising a first curved face and an opposing second curved face is described. The first and second curved faces are arranged to provide the nonlinear crystal with rotational symmetry about at least one axis of the nonlinear crystal. The nonlinear crystal allows for frequency tuning of a generated optical field that is generated by propagating a fundamental optical field through the nonlinear crystal by rotation of the nonlinear crystal about an axis of rotation without any significant, or minimal, deviation being introduced to the generated optical field.

Abstract: An apparatus and method are provided for managing a capability domain. The apparatus has processing circuitry for executing instructions, the processing circuitry when in a default state being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is also provided to store a program counter capability used by the processing circuitry to determine a program counter value. The program counter capability is arranged to identify a capability state for the processing circuitry. The processing circuitry is then arranged, when the capability state indicates the default state, to operate in the capability domain. However, when the capability state indicates the executive state, the processing circuitry is arranged to operate in a manner less constrained than when in the default state so as to allow modification of the capability domain.

Abstract: An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p?q?e bits of the lower limit and the upper limit is derivable from the most significant p?q?e bits of the pointer value.