Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: An imaging system may include an array of pixels that each generates pixel data and a pixel data compression system. The pixel data compression system may include pixel data to variable-precision floating-point conversion circuitry, discrete wavelet transform circuitry, encoding circuitry, and serialization circuitry. The pixel data to variable-precision floating-point conversion circuitry may generate bits associated with a floating-point representation of the pixel data. The bits associated with the floating-point representation may include a sign component, an exponent component, and a mantissa component. The exponent component may be offset by a value to generate the floating-point value associated with the pixel data.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: An imaging system may include an array of pixels that each generates pixel data and a pixel data compression system. The pixel data compression system may include pixel data to variable-precision floating-point conversion circuitry, discrete wavelet transform circuitry, encoding circuitry, and serialization circuitry. The pixel data to variable-precision floating-point conversion circuitry may generate bits associated with a floating-point representation of the pixel data. The bits associated with the floating-point representation may include a sign component, an exponent component, and a mantissa component. The exponent component may be offset by a value to generate the floating-point value associated with the pixel data.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

Abstract: Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

Abstract: Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

Abstract: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.

Abstract: Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

Abstract: A self calibrating stereo camera includes first and second spatial transform engines for directly receiving first and second images, respectively, of an object. The first and second spatial transform engines are coupled to a stereo display for displaying a fused object in stereo. A calibration module is coupled to the first and second spatial transform engines for aligning the first and second images, prior to display to a viewer. The first and second point extracting modules, respectively, receive the first and second images for extracting interest points from each image. A matching points module is coupled to the first and second point extracting modules for matching the interest points extracted by the first and second point extracting modules. The calibration module determines alignment error between the first and second images, in response to the interest point matches calculated by the matching points module.