Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

Abstract: The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

Abstract: A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided in which multiple PEs share their connections to multiple data bits in the memory array. Each PE is associated with a plurality of memory buffer registers, which stores data read from (or to be written to) one or two memory data bits. In horizontal (normal) mode connection the memory bits are selected so that all the bits of a given byte are stored in the same PE, i.e., each set of buffer registers associated with a respective PE contains one byte as seen by an external device. In vertical (bit serial) mode, each set of buffer registers contains the successive bits at successive locations in the memory corresponding to that PEs position in the memory word.

Abstract: A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time. In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.

Abstract: A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided in which multiple PEs share their connections to multiple data bits in the memory array. Each PE is associated with a plurality of memory buffer registers, which stores data read from (or to be written to) one or two memory data bits. In horizontal (normal) mode connection the memory bits are selected so that all the bits of a given byte are stored in the same PE, i.e., each set of buffer registers associated with a respective PE contains one byte as seen by an external device. In vertical (bit serial) mode, each set of buffer registers contains the successive bits at successive locations in the memory corresponding to that PEs position in the memory word.

Abstract: The processing elements of a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significant alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

Abstract: A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time, In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.

Abstract: A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a memory interface, a program memory coupled to the memory interface, and a plurality of memory/processing units coupled to the memory interface and the program memory. Each of the memory/processing units includes a system memory and a processor coupled to the respective system memory. Instructions for the processors are transferred to the program memory and stored in the program memory responsive to a first set of addresses on the address bus of the mother-board. The processors then execute the instructions from the program memory, and may access the system memory during execution of the instructions. The system memory may also be accessed through the data bus of the mother-board responsive to a second set of addresses on the address bus of the mother-board.

Abstract: A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transfer data between PEs in the MPP is disclosed. A register having a data width equal to the data width of the PE for holding data for movement from one PE to another is provided in each PE. The register can be loaded in parallel within the PE, and operated as a shift register to transfer a fill data width word from one PE to another PE using a 1-bit wide serial interconnection.

Abstract: A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings between a PE sub-array and its associated memory stripe are managed by placing the PE sub-arrays so that their data paths run at right angle to the data paths of the plurality of memory stripes. The data lines exiting the memory stripes are run across the PE sub-arrays on one metal layer. At the appropriate locations, the data lines are coupled to another orthogonally oriented metal layer to complete the coupling between the memory stripe and its associated PE sub-array. The plurality of PE sub-arrays are mapped to form a large logical array, in which each PE is coupled to four other PEs. Physically distant PEs are coupled using current mode differential logical couplings an drivers to insure good signal integrity at high operational speeds. Each PE contains a small DRAM register array.

Abstract: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.

Abstract: An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. The active memory device includes a vector processing and re-ordering system coupled to the array control unit and the memory device. The vector processing and re-ordering system re-orders data received from the memory device into a vector of contiguous data, process the data in accordance with an instruction received from the array control unit to provide results data, and passes the results data to the memory device.

Abstract: An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical columns. The array is logically folded to minimize the length of the longest path between processing elements by physically interleaving the processing elements so that the processing elements in different logical rows a physically interleaved with each other and the processing elements in different logical columns a physically interleaved with each other.

Abstract: A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DRAM control unit (“DCU”) commands to a DRAM control unit or array control unit (“ACU”) commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in the ACU where processing array instructions are stored. The processing array instructions are used to address a decode SRAM containing microinstructions that are used to control the operation of an array of processing elements. The number of bits in each of the microinstructions is substantially greater than the number of bits in the corresponding processing array instruction. The decode SRAM is preferably loaded prior to operation of the active memory based on the operations to be performed by the processing elements.

Abstract: A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

Abstract: A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a memory interface, a program memory coupled to the memory interface, and a plurality of memory/processing units coupled to the memory interface and the program memory. Each of the memory/processing units includes a system memory and a processor coupled to the respective system memory. Instructions for the processors are transferred to the program memory and stored in the program memory responsive to a first set of addresses on the address bus of the mother-board. The processors then execute the instructions from the program memory, and may access the system memory during execution of the instructions. The system memory may also be accessed through the data bus of the mother-board responsive to a second set of addresses on the address bus of the mother-board.