Abstract: A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transfer data between PEs in the MPP is disclosed. A register having a data width equal to the data width of the PE for holding data for movement from one PE to another is provided in each PE. The register can be loaded in parallel within the PE, and operated as a shift register to transfer a full data width word from one PE to another PE using a 1-bit wide serial interconnection.

Abstract: A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings between a PE sub-array and its associated memory stripe are managed by placing the PE sub-arrays so that their data paths run at right angle to the data paths of the plurality of memory stripes. The data lines exiting the memory stripes are run across the PE sub-arrays on one metal layer. At the appropriate locations, the data lines are coupled to another orthogonally oriented metal layer to complete the coupling between the memory stripe and its associated PE sub-array. The plurality of PE sub-arrays are mapped to form a large logical array, in which each PE is coupled to four other PEs. Physically distant PEs are coupled using current mode differential logical couplings an drivers to insure good signal integrity at high operational speeds. Each PE contains a small DRAM register array.

Abstract: The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a row select line connecting to all of the processing elements in the row. A processing element in the array may be selected by activation of its row and column select lines.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighbourhood connection register configured to receive data from and send data to other processing elements. The connections between the result registers and between the result registers and the neighbourhood connection register are selectively configurable by applied control signals.

Abstract: A memory core with an access time that does not include a delay associated with decoding address information. Address decode logic is removed from the memory core and the address decode operation is performed in an addressing pipeline stage that occurs during a clock cycle prior to a clock cycle associated with a memory access operation for the decoded address. After decoding the address in a first pipeline stage, the external decode logic drives word lines connected to the memory core in a subsequent pipeline stage. Since the core is being driven by word lines, the appropriate memory locations are accessed without decoding the address information within the core. Thus, the delay associated with decoding the address information is removed from the access time of the memory core.

Abstract: A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time. In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.

Abstract: A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means comprising one or more scan chains or serially connected registers for access by an external host computer system. The procedure comprises: a) the host computer system carrying out a debug procedure via said scan chains, and selectively interrupting such debug procedure for access to a peripheral memory mapped device; b) the host computer system writing into an area or memory of the processor a program for reading and/or writing data at a specified memory location; and c) the host computer system causing said processor to run said program, and then to return to said debug procedure.

Abstract: A memory core with an access time that does not include a delay associated with decoding address information. Address decode logic is removed from the memory core and the address decode operation is performed in an addressing pipeline stage that occurs during a clock cycle prior to a clock cycle associated with a memory access operation for the decoded address. After decoding the address in a first pipeline stage, the external decode logic drives word lines connected to the memory core in a subsequent pipeline stage. Since the core is being driven by word lines, the appropriate memory locations are accessed without decoding the address information within the core. Thus, the delay associated with decoding the address information is removed from the access time of the memory core.

Abstract: The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: The processing elements of a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: A memory core with an access time that does not include a delay associated with decoding address information. Address decode logic is removed from the memory core and the address decode operation is performed in an addressing pipeline stage that occurs during a clock cycle prior to a clock cycle associated with a memory access operation for the decoded address. After decoding the address in a first pipeline stage, the external decode logic drives word lines connected to the memory core in a subsequent pipeline stage. Since the core is being driven by word lines, the appropriate memory locations are accessed without decoding the address information within the core. Thus, the delay associated with decoding the address information is removed from the access time of the memory core.

Abstract: A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.

Abstract: In order to smooth the entry into a debugging operation using a scan chain of registers in a microprocessor, a method for carrying out debugging procedures. The method comprises providing a processor with a chain of scan registers, a scan interface for interfacing with an external scan controller, a breakpoint interrupt mechanism for executing an interrupt instruction, and a processor clock control mechanism. The method includes detecting or generating a breakpoint in the operation of the processor. The breakpoint interrupt mechanism executes an interrupt instruction as a result of which the processor completes its current instruction, and signals the same to the scan interface. The scan interface asserts a Start Scan signal to the clock signal control mechanism, which whereupon stops the processor clock or clocks. The external scan controller is alerted to start a scan sequence.

Abstract: A memory core with an access time that does not include a delay associated with decoding address information. Address decode logic is removed from the memory core and the address decode operation is performed in an addressing pipeline stage that occurs during a clock cycle prior to a clock cycle associated with a memory access operation for the decoded address. After decoding the address in a first pipeline stage, the external decode logic drives word lines connected to the memory core in a subsequent pipeline stage. Since the core is being driven by word lines, the appropriate memory locations are accessed without decoding the address information within the core. Thus, the delay associated with decoding the address information is removed from the access time of the memory core.

Abstract: A memory core with an access time that does not include a delay associated with decoding address information. Address decode logic is removed from the memory core and the address decode operation is performed in an addressing pipeline stage that occurs during a clock cycle prior to a clock cycle associated with a memory access operation for the decoded address. After decoding the address in a first pipeline stage, the external decode logic drives word lines connected to the memory core in a subsequent pipeline stage. Since the core is being driven by word lines, the appropriate memory locations are accessed without decoding the address information within the core. Thus, the delay associated with decoding the address information is removed from the access time of the memory core.

Abstract: A controllable latch/register circuit for an integrated circuit comprises an input latch (30) coupled in series with an output latch (32). The latches are operated under control of a control circuit (34) having mode inputs. In one mode, the latches are operated as a non-transparent register; the output latch (32) holds the output stable while new data is inputted to the input latch (30); the output latch (32) is only opened once the input latch has been latched closed. In one or more other modes, the latches are operated as a single controllable transparent latch; for example, one or the latches (30) can be held permanently open such that operation of the circuit depends entirely on the state of the other latch (32).

Abstract: A computer system and method for generating a hardware description language source code file with embedded microcode segments for describing control logic of a complex digital system. A macro file is defined, comprising source code written in the hardware description language and a macro name associated with a segment of the source microcode in the macro file. A skeleton file is defined, comprising source code written in the hardware description language and including a reference to the macro name. The skeleton file is combined with the segment of the source microcode from the macro file at the reference to the macro name using a preprocessor to form a final source code file. Preferably, each microcode segment is encapsulated between a pair of comment statements expressed in the hardware description language.