Patents by Inventor Grant Kloster

Grant Kloster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sealing porous dielectrics with silane coupling reagents
    Publication number: 20050020074
    Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.
    Type: Application
    Filed: July 25, 2003
    Publication date: January 27, 2005
    Inventors: Grant Kloster, Chih-I Wu, Xiaorong Morrow
  • PROTECTING METAL CONDUCTORS WITH SACRIFICIAL ORGANIC MONOLAYERS
    Publication number: 20050020058
    Abstract: A structure and method for protecting exposed copper lines with chemisorbed, sacrificial, organic monolayers from further processing steps are herein described.
    Type: Application
    Filed: July 25, 2003
    Publication date: January 27, 2005
    Inventors: David Gracias, Grant Kloster
  • Method of making semiconductor devices using carbon nitride, a low-dielectric-constant hard mask and/or etch stop
    Publication number: 20040119163
    Abstract: A method for making a semiconductor device using carbon nitride as an etch stop diffusion barrier and/or a hard mask is described. An interconnect structure is made by at least: forming an etch stop diffusion layer, depositing an interlayer dielectric, etching necessary vias and trenches, forming a barrier layer, forming copper alloy, and planarizing. The use of a hard mask in the method is optional. The etch stop diffusion layer, the optional hard mask, or both comprised by carbon nitride.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Lawrence Wong, Jihperng Leu, Grant Kloster, Andrew W. Ott, Patrick Morrow
  • Plating a conductive material on a dielectric material
    Publication number: 20040104483
    Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.
    Type: Application
    Filed: November 26, 2003
    Publication date: June 3, 2004
    Inventors: Michael D. Goodner, Grant Kloster, Steven W. Johnston
  • Selectively growing a polymeric material on a semiconductor substrate
    Publication number: 20040087183
    Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventors: Michael D. Goodner, Grant Kloster
  • Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material
    Publication number: 20040063305
    Abstract: An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 1, 2004
    Inventors: Grant Kloster, Jihperng Leu, Hyun-Mog Park
  • Low-k dielectric film with good mechanical strength
    Publication number: 20040026783
    Abstract: The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; forming an opening in the dielectric; and forming a conductor in the opening.
    Type: Application
    Filed: August 12, 2002
    Publication date: February 12, 2004
    Inventors: Grant Kloster, Lee Rockford, Jihperng Leu
  • Plating a conductive material on a dielectric material
    Patent number: 6682989
    Abstract: A surface may be selectively coated with a polymer using an induced surface grafting or polymerization reaction. The reaction proceeds in those regions that are polymerizable and not in other regions. Thus, a semiconductor structure having organic regions and metal regions exposed, for example, may have the organic polymers formed selectively on the organic regions and not on the unpolymerizable or metal regions.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: January 27, 2004
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Grant Kloster, Steven W. Johnston
  • Method of making semiconductor device using a novel interconnect cladding layer
    Publication number: 20030186535
    Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Lawrence D. Wong, Jihperng Leu, Grant Kloster, Andrew Ott, Patrick Morrow
  • Method of making a semiconductor device using a damascene interconnect with a laminated dielectric
    Publication number: 20030173651
    Abstract: A method of fabricating a semiconductor device includes laminating a dielectric sheet on a substrate and forming a via opening in the dielectric sheet. The method further includes depositing a conductive material into the first via opening.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 18, 2003
    Inventors: Lawrence D. Wong, Jihperng Leu, Grant Kloster, Andrew Ott, Patrick Morrow
  • Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
    Publication number: 20030064607
    Abstract: A method to improve nucleation and/or adhesion of a CVD or ALD-deposited film/layer onto a low-dielectric constant (low-k) dielectric layer, such as a polymeric dielectric or a carbon-doped oxide. In an embodiment, the method includes providing a substrate into a deposition chamber. A dielectric layer having a reactive component is formed over the substrate. The formed dielectric layer having the reactive component is then processed to produce polar groups or polar sites at least on a surface of the formed dielectric layer.
    Type: Application
    Filed: September 29, 2001
    Publication date: April 3, 2003
    Inventors: Jihperng Leu, Chih-I Wu, Ying Zhou, Grant Kloster
  • Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
    Publication number: 20020140103
    Abstract: The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Inventors: Grant Kloster, Jihperng Leu, Lawrence Wong, Andrew Ott, Patrick Morrow