Patents by Inventor Grant M. Kloster
Grant M. Kloster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7239019Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: June 28, 2005Date of Patent: July 3, 2007Assignee: Intel CorporationInventors: Jihperng Leu, Grant M. Kloster, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns
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Patent number: 7220668Abstract: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.Type: GrantFiled: June 28, 2005Date of Patent: May 22, 2007Assignee: Intel CorporationInventors: Hyun-Mog Park, Boyan Boyanov, Grant M. Kloster, Vijayakumar S. RamachandraRao
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Patent number: 7179755Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.Type: GrantFiled: December 30, 2004Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: Boyan Boyanov, Grant M. Kloster, Vijay Ramachandrarao, Hyun-Mog Park
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Patent number: 7180180Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layers of compliant material, and assembling the substrate into a stacked semiconductor device.Type: GrantFiled: March 30, 2004Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: Grant M. Kloster, Michael D. Goodner, Shriram Ramanathan, Patrick Morrow
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Patent number: 7169715Abstract: In one embodiment, the present invention includes introducing a conventional precursor and an organic precursor having an organic porogen into a vapor deposition apparatus; and forming a dielectric layer having the organic porogen on a substrate within the vapor deposition apparatus from the precursors. In certain embodiments, at least a portion of the organic porogen may be removed after subsequent processing, such as dual damascene processing.Type: GrantFiled: March 21, 2003Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: Andrew W. Ott, Grant M. Kloster, Robert P. Meagley, Michael D. Goodner
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Patent number: 7138158Abstract: In one embodiment, the present invention includes introducing a precursor containing hydrocarbon substituents and optionally a second conventional or hydrocarbon-containing precursor into a vapor deposition apparatus; and forming a dielectric layer having the hydrocarbon substituents on a substrate within the vapor deposition apparatus from the precursor(s). In certain embodiments, at least a portion of the hydrocarbon substituents may be later removed from the dielectric layer to reduce density thereof.Type: GrantFiled: February 28, 2003Date of Patent: November 21, 2006Assignee: Intel CorporationInventors: Robert P. Meagley, Michael D. Goodner, Andrew W. Ott, Grant M. Kloster, Michael L. McSwiney, Bob E. Leet
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Patent number: 7087538Abstract: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.Type: GrantFiled: August 16, 2004Date of Patent: August 8, 2006Assignee: Intel CorporationInventors: David Staines, Grant M. Kloster, Shriram Ramanathan
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Patent number: 7034399Abstract: A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.Type: GrantFiled: February 19, 2004Date of Patent: April 25, 2006Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'Brien, Justin K. Brask, Michael D. Goodner, Donald Bruner
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Patent number: 7018918Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: November 3, 2003Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'brien, Michael D. Goodner, Jihperng Leu, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns
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Patent number: 6992391Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.Type: GrantFiled: September 28, 2001Date of Patent: January 31, 2006Assignee: Intel CorporationInventors: Andrew Ott, Lawrence Wong, Patrick Morrow, Jihperng Leu, Grant M. Kloster
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Patent number: 6984873Abstract: Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.Type: GrantFiled: December 5, 2003Date of Patent: January 10, 2006Assignee: Intel CorporationInventors: Grant M. Kloster, David Staintes, Shriram Ramanathan
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Publication number: 20050272248Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying permeable material. As a result, at least one void is created, contributing to desirable dielectric characteristics.Type: ApplicationFiled: July 19, 2005Publication date: December 8, 2005Inventors: Grant M. Kloster, Xiarong Morrow, Jihperng Leu
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Patent number: 6946384Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layer of complaint material, and assembling the substrate into a stacked semiconductor device.Type: GrantFiled: June 6, 2003Date of Patent: September 20, 2005Assignee: Intel CorporationInventors: Grant M. Kloster, Michael D. Goodner, Shriram Ramanathan, Patrick Morrow
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Patent number: 6943121Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.Type: GrantFiled: November 21, 2002Date of Patent: September 13, 2005Assignee: Intel CorporationInventors: Jihperng Leu, Grant M. Kloster, David H. Gracias, Lee D. Rockford, Peter K. Moon, Chris E. Barns
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Patent number: 6930391Abstract: An electroplated metal alloy including at least three elements. A multilayer interconnection structure that includes a substrate that is an interior of the interconnection structure, a conductive seed layer exterior to the substrate, and an electroplated metal alloy layer including at least three elements exterior to the conductive seed layer. A multilayer interconnection structure formed on a substrate, that includes a barrier layer, and a conductive seed layer, wherein the improvement includes an electroplated metal alloy layer including at least three elements. A method for forming a multilayer interconnection structure that includes providing a substrate, depositing a conductive seed layer, and electroplating a metal alloy layer including at least three elements exterior to the conductive seed layer.Type: GrantFiled: August 27, 2002Date of Patent: August 16, 2005Assignee: Intel CorporationInventors: Grant M. Kloster, Sean J. Hearne
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Patent number: 6903461Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.Type: GrantFiled: December 18, 2003Date of Patent: June 7, 2005Assignee: Intel CorporationInventors: Grant M. Kloster, Jihperng Leu, Hyun-Mog Park
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Patent number: 6861332Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.Type: GrantFiled: November 21, 2002Date of Patent: March 1, 2005Assignee: Intel CorporationInventors: Hyun-Mog Park, Grant M. Kloster
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Patent number: 6846755Abstract: A dielectric material is strengthened by bonding a metal component to the dielectric matrix. The metal component may be a metal oxide or metal oxide precursor. The metal component may be deposited on the substrate with the dielectric material, or sol-gel chemistry may be used and the liquid solution spin-coated on a substrate.Type: GrantFiled: February 18, 2003Date of Patent: January 25, 2005Assignee: Intel CorporationInventors: Grant M. Kloster, Jihperng Leu
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Publication number: 20040256724Abstract: Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.Type: ApplicationFiled: December 5, 2003Publication date: December 23, 2004Inventors: Grant M. Kloster, David Staintes, Shriram Ramanathan
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Publication number: 20040256736Abstract: Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.Type: ApplicationFiled: June 20, 2003Publication date: December 23, 2004Inventors: Grant M. Kloster, David Staintes, Shriram Ramanathan