Patents by Inventor Greg A. Dyck

Greg A. Dyck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020120827
    Abstract: An exemplary embodiment of the invention is a virtual memory structure having a first virtual memory space and a virtual page frame table space. The first virtual memory space includes at least one private area and at least one common area. The virtual page frame table space is separate from the first virtual memory space. The virtual page frame table space includes at least one page frame table entry representing a frame of real memory.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Applicant: International Business Machines Corporation
    Inventors: Harris M. Morgenstern, Greg A. Dyck, Danny R. Sutherland
  • Publication number: 20020120808
    Abstract: In a computing system implementing a virtual memory system having real memory storage frames for storing virtual pages of data and an auxiliary storage system comprising auxiliary storage slots for storing copies of corresponding virtual pages provided in real storage frames, a system and method for freeing auxiliary storage slots to enable further copying of pages thereto.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Inventors: Greg A. Dyck, Harris M. Morgenstern, Danny R. Sutherland, Wendy L. Wang
  • Patent number: 6336184
    Abstract: A central processing unit of an information handling system is provided with a Trap instruction to facilitate transfer of control from a user program to a trap program. A dispatchable unit control block (DUCT) of the CPU is loaded with the address of a trap control block, which in turn contains the addresses of a trap save area and a trap program. The user program is provided with Trap instructions at the desired transfer points. Upon decoding a Trap instruction in the user program, the CPU saves state information from the program status word (PSW), general registers and access registers in the designated trap save area, loads the address of the trap control block into a general register, and copies the address of the trap program into the instruction address field of the PSW to transfer control to the trap program. Upon completion of execution, the trap program may issue a Resume Program (RP) instruction to restore the previously saved state information to return control to the user program.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: January 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Gregory A. Burke, Greg A. Dyck, David E. Lee, Brian B. Moore, Steven J. Repka