Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: Disclosed herein are various embodiments of a graphics accelerator, which may include an integrated circuit. The integrated circuit may include a local memory; a direct memory access (DMA) engine; a processor; and one or more processing pipelines. The local memory stores graphics data that includes a plurality of pixels. The DMA engine transfers the graphics data between the local memory and an external memory. The processor performs at least one operation, in parallel, on components of at least a portion of the pixels. The one or more processing pipelines process the graphics data. The graphics accelerator works on operands and produces outputs for one set of pixels while the DMA engine is bringing in operands for a future set of pixel operations, and transfers data from the external memory to the one or more processing pipelines by directing data to the one or more pipelines.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A system and method are used to generate pseudo MPEG information from digital video information. An artificial time stamp module and a data transport device can be used to generate the pseudo MPEG information, including associating an artificial time stamp with the digital video information. This pseudo MPEG information can be decoded as MPEG information.

Abstract: A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.

Abstract: A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: A system and method that support display of video fields using related data encoded in data structures. Each data structure is associated with one video field and contains all the information associated with the display of the video field. The data structure is encoded with the video field that is displayed exactly one field prior to the field associated with the data structure. In an embodiment of the present invention, the data structure contains all the information associated with the display of a video field, regardless of whether certain data changes from one field to the next.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.