Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A digital filter (20,30) separates an M-bit (12) chrominance component (C12) from an N-bit (8) digital composite video signal (CV) supplied thereto, M (12) being greater than N (8) due to arithmetic operations (24,44,46,50) required for the separation. The separated M bit chrominance component is reduced to N-bits and subtracted from the composite video signal to provide a separated luminance component. For bit reduction, the separated chrominance component (C12) is subjected to symmetrical rounding (100A or 100B and 104) and limiting (104). Advantageously, symmetrical rounding of the chrominance component provides reduces a tendency for the luminance component to exhibit contouring when displayed.

Abstract: A video display control system comprises: a video display having a wide format display ratio; a letterbox detector for sampling video information in pictures represented by input video signals having a letterbox format and generating a control signal for enlarging the pictures for substantially filling the video display means with active video; and, a first control circuit for restricting operation of the letterbox detector to a vertical range of horizontal lines in each field of the video signal; and, a second control circuit for restricting operation of the letterbox detector to a horizontal range of video data in each of the horizontal lines.

Abstract: Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory. A second line memory in a parallel signal path processes video chrominance data from the video signal. A control circuit generates respective timing signals for writing data into each of the first and second memories and for reading data from each of first and second the line memories. A timing delay circuit for the control circuit, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During the expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values.

Abstract: Apparatus for measuring skew in a clock signal for processing a video signal includes a cascade connection of a plurality of analog delay elements to which the clock signal is applied. The output connections of each analog delay element is coupled to a data input terminal of a respective storage element. A signal representative of the horizontal synchronizing signal is applied to the storage elements to simultaneously latch signal into the respective storage elements, thereby capturing a representative cycle of the sampling clock signal in the storage elements. Decoding circuitry is coupled to the storage elements for detecting the relative position of the e.g., leading transition of the sampling clock pulse immediately preceding the trailing transition of the horizontal pulse A ratio is calculated indicative of the skew error, which ratio corresponds to the position of the first transition, in units of delay, divided by the duration of the sampling clock period, in units of delay.

Abstract: A video display control system automatically controls a video display responsive to detection of letterbox format input video signals having varying format display ratios. A detection circuit continuously detects the first and last lines of active video in a video signal. A memory stores scan line numbers corresponding to the first and last lines of active video. The height of the picture is determined from the scan line numbers of the first and last lines of active video. The picture height is indicative of the format display ratio of the letterbox input. A comparator circuit compares the picture height to a threshold corresponding to the widest expected format display ratio of a letterbox input signal.

Abstract: A video display control system, comprises a video display having a first format display ratio. A picture height circuit determines an active video picture height from an input video signal having a second format display ratio. A detector circuit identifies letterbox formats responsive to the active video picture height in the video signal and determines a format display ratio of the letterbox picture. A zoom control circuit is operable in a first mode of operation for enlarging the picture in size to fill the display substantially entirely, notwithstanding consequent cropping of the picture, and operable in a second mode of operation for enlarging the picture in size to substantially fill the display vertically, notwithstanding consequent unused portions of the display. A vertical pan control circuit automatically centers the picture in both modes of operation.