Patents by Inventor Greg C. Baldwin
Greg C. Baldwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8609483Abstract: Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.Type: GrantFiled: June 28, 2010Date of Patent: December 17, 2013Assignee: Texas Instruments IncorporatedInventors: Kamel Benaissa, Greg C. Baldwin
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Patent number: 8604543Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.Type: GrantFiled: June 29, 2012Date of Patent: December 10, 2013Assignee: Texas Instruments IncorporatedInventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath
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Patent number: 8405154Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.Type: GrantFiled: June 23, 2011Date of Patent: March 26, 2013Assignee: Texas Instruments IncorporatedInventors: Kamel Benaissa, Greg C. Baldwin, Shaofeng Yu, Shashank S. Ekbote
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Patent number: 8344479Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: GrantFiled: February 15, 2011Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Greg C. Baldwin
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Publication number: 20120261766Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.Type: ApplicationFiled: June 29, 2012Publication date: October 18, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kamel BENAISSA, Greg C. BALDWIN, Vineet MISHRA, Ananth KAMATH
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Patent number: 8232158Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.Type: GrantFiled: June 28, 2010Date of Patent: July 31, 2012Assignee: Texas Instruments IncorporatedInventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath
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Patent number: 8114729Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.Type: GrantFiled: October 10, 2007Date of Patent: February 14, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Ekbote, Kamel Benaissa, Greg C. Baldwin, Borna Obradovic
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Publication number: 20110248347Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.Type: ApplicationFiled: June 23, 2011Publication date: October 13, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kamel BENAISSA, Greg C. BALDWIN, Shaofeng YU, Shashank S. EKBOTE
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Patent number: 7994009Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.Type: GrantFiled: June 26, 2009Date of Patent: August 9, 2011Inventors: Kamel Benaissa, Greg C. Baldwin, Shaofeng Yu, Shashank S. Ekbote
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Publication number: 20110156144Abstract: An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.Type: ApplicationFiled: June 28, 2010Publication date: June 30, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kamel Benaissa, Greg C. Baldwin, Vineet Mishra, Ananth Kamath
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Publication number: 20110133880Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: ApplicationFiled: February 15, 2011Publication date: June 9, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert L. Pitts, Greg C. Baldwin
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Patent number: 7888227Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: GrantFiled: June 12, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Greg C. Baldwin
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Publication number: 20100327374Abstract: An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Inventors: Kamel Benaissa, Greg C. Baldwin, Shaofeng Yu, Shashank S. Ekbote
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Publication number: 20100327361Abstract: An integrated circuit is disclosed containing two types of MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Inventors: KAMEL BENAISSA, Greg C. Baldwin, Shaofeng Yu
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Publication number: 20100327335Abstract: Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow.Type: ApplicationFiled: June 28, 2010Publication date: December 30, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kamel BENAISSA, Greg C. BALDWIN
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Patent number: 7718482Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.Type: GrantFiled: October 30, 2007Date of Patent: May 18, 2010Assignee: Texas Instruments IncorporatedInventors: Shashank Ekbote, Borna Obradovic, Greg C. Baldwin
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Publication number: 20090098694Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.Type: ApplicationFiled: October 30, 2007Publication date: April 16, 2009Applicant: Texas Instruments IncorporatedInventors: Shashank Ekbote, Borna Obradovic, Greg C. Baldwin
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Publication number: 20090096031Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.Type: ApplicationFiled: October 10, 2007Publication date: April 16, 2009Applicant: Texas Instruments IncorporatedInventors: Shashank EKBOTE, Kamel Benaissa, Greg C. Baldwin, Borna Obradovic
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Publication number: 20080286933Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: ApplicationFiled: June 12, 2008Publication date: November 20, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert L. Pitts, Greg C. Baldwin
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Patent number: 7400025Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).Type: GrantFiled: May 11, 2004Date of Patent: July 15, 2008Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Greg C. Baldwin