Abstract: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

Abstract: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125) and an optional patterned silicon oxide layer (135) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (170) during the formation of metal silicide regions (160) on the integrated circuit resistor (170).

Abstract: An integrated circuit resistor (150) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (74) is formed on the surface of the resistor polysilicon layer (40) that functions to mask the surface of the integrated circuit resistor (150) during the formation of metal silicide regions (140) on the integrated circuit resistor (150).

Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2) , a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

Abstract: An integrated circuit containing a resistor and the resistor per se. The circuit includes a substrate (2), a semiconductor resistor (3) on the substrate and a layer of electrically insulating material (5) disposed over the substrate and the semiconductor resistor having at least one contact (11, 13, 15) extending therethrough to the semiconductor resistor, the contact having an electrical path therein extending to and forming an interface with an end portion of the semiconductor resistor. The semiconductor resistor has a semiconductor resistor body, preferably of doped polysilicon, having one of a positive or negative temperature coefficient of resistance and a resistor head. The resistor head consists essentially of the electrical path which is metal interconnect, the contacts and then interface to and from the resistor body and in contact with the resistor body, the resistor head having the other of a positive or negative temperature coefficient of resistance.

Abstract: A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.