Abstract: A method for controlling data transfers through a computer system is provided. First information is transferred to a first node of the computer system regarding availability of a first data storage area within a second node of the computer system for data to be transferred through the second node. Also transferred to the first node is second information regarding availability of a second data storage area within the second node for data to be consumed within the second node. The first information and the second information are then processed to determine if data within the first node destined for the second node is to be transferred to the second node.

Abstract: A method for employing an interconnection fabric of a computer system including a first endnode and a second endnode is provided. A first transaction is transferred from the first endnode toward the second endnode over a primary path of the fabric. The first transaction is retransferred from the first endnode toward the second endnode over an alternate path of the fabric after a period of time after transferring the first transaction. An acknowledgement of the first transaction being received by the second endnode over the primary path is transferred to the first endnode after retransferring the first transaction. A second transaction from the first endnode toward the second endnode is transferred solely over the primary path after the acknowledgement is received by the first endnode.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.

Abstract: A method, system, and apparatus for testing a scalable computer system is provided. In an illustrative implementation, the system comprises a first buffer, a sequence stored in the first buffer, and a state controller for monitoring a communications link for a trigger signal. Upon detection of the trigger signal, the state controller causes the sequence stored in the first buffer to be inserted in the link.

Abstract: A method, system, and apparatus for testing a scalable computer system is provided. In an illustrative implementation, a system for testing a scalable computer system includes configuring a single cell on a partitionable system to create an isolated test channel. A test packet is generated and provided to the test channel. The test channel inserts the test packet into the scalable computer system via a communications link, and a response to the insertion of the test packet is monitored to determine system performance.

Abstract: A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: Methods and apparatus in a partitionable computing system. A first link controller is associated with a first partition. A second link controller is associated with a second partition. A computing element communicated with link controllers to establish or deny communication between the partitions.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: A partitionable computer system and method of operating the same is disclosed. The partitionable computer system has a state machine, a processor, and a device controller. The state machine can be configured to monitor the status of a partition of the partitionable computer system. The information provided by the state machine can be used to provide security within the partitionable computing system.

Abstract: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Abstract: An optimized storage system is implemented in a processor that executes instructions out of order. The system minimizes storage requirements for dependency operands in the processor by eliminating a need for separate storage mechanisms for holding different dependency operands that are produced from different instructions. The system comprises the following elements. An instruction reordering mechanism is configured to permit execution of the instructions in an out of order sequence. Rename registers (RRs) are associated with the reordering mechanism. Logic causes storage of trap information in the rename registers intermixed with instruction execution results. The trap information may be associated with arithmetic integer or floating point (fp) operations and can include the identity of the trapped instruction, the trapped operation, etc. Logic further causes storage of different sized dependency operands within the RRs.