Abstract: An optimized storage system is implemented in a processor that executes instructions out of order. The system comprises the following elements. An instruction reordering mechanism is configured to permit execution of the instructions in an out of order sequence. Rename registers (RRs) are associated with the reordering mechanism. Logic causes storage of trap information in the rename registers intermixed with instruction execution results. The trap information may be associated with arithmetic integer or floating point (fp) operations and can include the identity of the trapped instruction, the trapped operation, etc. Logic further causes storage of different sized dependency operands within the RRs. The dependency operands can include, for example, carry borrow (cb) operands and/or shift amount register (sar) operands. The dependency operands are produced by instructions and stored in the rename registers and are also retrieved and utilized by instructions.

Abstract: A panic trap system recovers from inaccurate results produced from out of order execution of instructions in a processor. The panic trap system includes a fetch mechanism (IFETCH) that fetches instructions from an instruction cache. Two queues receive the instructions from the fetch mechanism and execute the instructions out of order. Specifically, an ALU instruction queue (AQUEUE) receives instructions that are directed to the ALU. A memory instruction queue (MQUEUE) receives instructions that are directed to a data cache (DCACHE) or a main memory. The MQUEUE includes instruction registers and corresponding address reorder buffer slots (ARBSLOTs) for receiving memory instructions and data addresses corresponding to the results of instruction execution, respectively. Trap indicator logic is associated with each ARBSLOT for recognizing an architecturally incorrect execution of a memory instruction and for associating a nonarchitectural panic trap indicator with the instruction after execution.

Abstract: A system for recovering most recent writer status when a mispredicted branch occurs in a processor that executes instructions out of order. A queue holds instructions stored in the order they are fetched from memory. Each slot in the queue stores a target register that will receive the results of the instruction, and a most recent writer status bit indicating whether the slot is the last instruction to write to the target register. When inserting a new instruction, each slot compares the target register of the new instruction to its target register, and when a match occurs, the slot resets its most recent writer status, and stores the new instruction slot number as a target taker. When a mispredicted branch occurs, the slot compares the mispredicted branch slot to the target taker slot, and when the target taker slot is greater, the slot regains the most recent writer status.

Abstract: A store-to-load (ST/LD) hazard resolution system for resolving conflicts produced from ST/LD instruction dependencies and out of order execution of instructions in a processor. The ST/LD hazard resolution system involves the following components. A fetch mechanism (IFETCH) fetches instructions from an instruction cache (ICACHE). A memory instruction queue (MQUEUE) receives instructions that are directed to a data cache (DCACHE) or a main memory from the IFETCH and executes the instructions out of order. The MQUEUE includes instruction registers and corresponding address reorder buffer slots (ARBSLOTs) for receiving memory instructions and data addresses corresponding to the results of instruction execution, respectively. A ST/LD hazard resolution system is associated with each ARBSLOT for recognizing and tracking ST/LD dependencies among the memory instructions.

Abstract: An instruction nullification system facilitates handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. Predictions are made as to whether instructions are dependent upon nullify instructions, such as a branch instruction. A dependent instruction can potentially be nullified by the nullify instruction. A dependent instruction is permitted to execute when it is predicted as not potentially nullified, regardless of when its corresponding nullify instruction commences execution.

Abstract: A fast nullify system and method facilitate handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution of an instruction by an execution unit, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. While instructions are executed in the reordering mechanism nullifying instructions and dependent instructions that can potentially be nullified by the nullifying instructions are identified. For each dependent instruction, a determination is made as to whether the dependent instruction qualifies for a fast nullify procedure in that the dependent instruction has less operands than a number that can be read by the execution unit.

Abstract: An address aggregation system enhances the performance of a processor that executes instructions out of order by enhancing the throughput of data addressing from the processor to a remote data cache (DCACHE). In essence, the processor is configured to concurrently address separate independent DCACHE banks, each preferably an inexpensive single ported random access memory (RAM), during each processor cycle. In the preferred implementation, the DCACHE has odd and even banks that are addressed by respective odd and even data addresses during each processor cycle. The processor comprises an instruction cache (ICACHE), an instruction fetch mechanism (IFETCH) for retrieving instructions from the ICACHE, a sort mechanism (SORT) for receiving instructions from the IFETCH and for sorting the instructions into arithmetic instructions and memory instructions, and a memory queue (MQUEUE) for receiving the memory instructions from the sort and permitting the instructions to execute out of order.

Abstract: An operand dependency tracking system monitors operand dependencies, among instructions in a processor that executes instruction out of order. The processor has queues that are configured to execute the instructions out of order. An arithmetic queue (aqueue) executes arithmetic instructions and a memory queue (mqueue) executes memory instructions. The aqueue has aslots for receiving respective instructions. Each aslot includes a set dependency latch, a use dependency latch, valid operand (valop) propagation logic, and valid dependent (valdep) logic. The set dependency latch produces a set dependency signal that indicates whether a local instruction in a local slot is to produce operand data that is to be used by a remote dependent instruction that follows the local instruction in program order.

Abstract: A miss tracking system optimizes the bandwidth to a main memory that is associated with a processor that utilizes a data cache and that executes instructions out of order. The miss tracking system includes the processor, the main memory in communication with the processor, and a data cache (DCACHE) associated with the processor. The processor has a memory queue (MQUEUE) for receiving and executing instructions that are directed to memory accesses to the DCACHE or the main memory. The MQUEUE includes a plurality of instruction processing mechanisms for receiving and executing respective memory instructions out of order. Each instruction processing mechanism includes an instruction register for storing an instruction and an address reorder buffer slot (ARBSLOT) for storing the data address of the instruction execution results.

Abstract: An operand dependency tracking system tracks operand dependencies among instructions in a processor that executes instructions out of order and that permits processing of multiple precision data words. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order.