Abstract: According to some implementations, a radio-frequency (RF) device includes a communication interface coupled to a serial bus. The RF device also includes a monitoring component coupled to the communication interface, the monitoring component configured to monitor the serial bus for first data transmitted to a first device coupled to the serial bus and configure the RF device based on the first data.

Abstract: A switch assembly for a radio frequency signal and corresponding radio frequency module and wireless device is disclosed. An example switch assembly comprises a first node coupled to an input of the switch assembly, a second node coupled to an output of the switch assembly, a first control node, and a common node; a first switch having a first plurality of transistors coupled between the first and second nodes, each transistor of the first plurality of transistors having a gate, a drain, and a source, each gate of the first plurality of transistors being coupled to the common node; a common resistor coupled between the first control node and the common node; and a second switch coupled between the first control node and the common node in parallel to the common resistor, the second switch configured to selectively bypass the common resistor.

Abstract: According to some implementations, a radio-frequency (RF) device includes a communication interface coupled to a serial bus. The RF device also includes a monitoring component coupled to the communication interface, the monitoring component configured to monitor the serial bus for first data transmitted to a first device coupled to the serial bus and configure the RF device based on the first data.

Abstract: According to some implementations, a radio-frequency (RF) device includes a communication interface coupled to a serial bus. The RF device also includes a monitoring component coupled to the communication interface, the monitoring component configured to monitor the serial bus for first data transmitted to a first device coupled to the serial bus and configure the RF device based on the first data.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

Abstract: Feedback compensation for multistage amplifiers. In some embodiments, an amplifier can include a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier can further include a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier can further include a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback pack can include a transconductance element and a second capacitance arranged in series. In some embodiments, such an amplifier can be configured as an operational-amplifier.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

Abstract: Feedback compensation for multistage amplifiers. In some embodiments, an amplifier can include a first stage, a second stage, and a third stage implemented in series between an input node and an output node. The amplifier can further include a first feedback path implemented between an output of the third stage and a node between the first and second stages, with the first feedback including a first capacitance. The amplifier can further include a second feedback path implemented between the output of the third stage and an output of the second stage. The second feedback pack can include a transconductance element and a second capacitance arranged in series. In some embodiments, such an amplifier can be configured as an operational-amplifier.

Abstract: According to some implementations, a radio-frequency (RF) device includes a communication interface coupled to a serial bus. The RF device also includes a monitoring component coupled to the communication interface, the monitoring component configured to monitor the serial bus for first data transmitted to a first device coupled to the serial bus and configure the RF device based on the first data.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

Abstract: A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. The DLL is configured to avoid a perceived phase shift when the control voltage to a delay line is reset upon reaching a predetermined amount. Embodiments disclosed include a DLL, a radio receiver using the DLL, a circuit for resetting the DLL, a method for recovering a modulated radio signal, and a method of synchronizing a reference clock to a radio signal. The approach can allow for improved synchronization of the reference clock to a received radio signal during baseband frequency recovery.

Abstract: A method, algorithm, circuits, and/or systems for demodulation in an amplitude modulated (AM) radio receiver are disclosed. In one embodiment, a radio receiver can include an amplifier configured to receive a radio frequency (RF) input signal and a gain control signal, and provide an amplified signal, an automatic gain control (AGC) circuit configured to receive a high threshold comparator output and provide the gain control signal, a mixer configured to combine the amplified signal and a local oscillation signal and provide a mixed output, a high threshold comparator configured to compare the mixed output with a reference level and provide the high threshold comparator output, and a low threshold comparator configured to compare the mixed output with the reference level and provide an output of the radio receiver.

Abstract: A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. In one embodiment, a receiver circuit can include: (i) a voltage-controlled oscillator (VCO) for providing a reference clock; (ii) a delay element that can receive the reference clock and provide a delay adjustment signal; (iii) a first channel for receiving a radio signal and providing a recovered radio signal from the radio signal and the delay adjustment signal, where the first channel includes a first mixer and a first filter; and (iv) a second channel for receiving the radio signal and a phase adjustment signal derived from the delay adjustment signal and for providing a delay control signal to the delay element from the radio signal and the phase adjustment signal, where the second channel includes a second mixer and a second filter.

Abstract: Apparatuses and methods for receiving an amplitude modulated signal in one of two modes depending on the quality of the received signal. In a first mode, the amplitude modulated signal is converted directly to a baseband signal. In a second mode, the amplitude modulated signal is converted to an intermediate frequency signal. The present invention advantageously combines direct conversion and image-rejection heterodyne receiver topologies with a relatively large degree of component reuse and relatively few additional components.

Abstract: A receiver for receiving an amplitude modulated (AM) signal may include a first and a second detector for detecting the maximum and minimum envelope values, respectively, of the received AM signal and an equalizer for periodically equalizing the maximum and minimum envelope values. A method for receiving an AM signal may include unidirectionally increasing a first output signal up to the maximum envelope value, unidirectionally decreasing a second output signal down to the minimum envelope value, and periodically equalizing the first and the second output signals.

Abstract: Apparatuses, circuits, and methods for receiving at least one radio signal in a radio controlled timing apparatus using a single timing source. The present invention advantageously eliminates the need to provide an additional timing source to receive at least one radio signal, and therefore reduces the material cost and eliminates many engineering challenges.

Abstract: A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. The DLL is configured to avoid a perceived phase shift when the control voltage to a delay line is reset upon reaching a predetermined amount. Embodiments disclosed include a DLL, a radio receiver using the DLL, a circuit for resetting the DLL, a method for recovering a modulated radio signal, and a method of synchronizing a reference clock to a radio signal. The approach can allow for improved synchronization of the reference clock to a received radio signal during baseband frequency recovery.

Abstract: Circuits, systems, and methods for generating a variable oscillator output. The circuits generally comprise a capacitor configured to receive first and second currents of a first polarity (e.g., charging currents) and a third current of a second polarity opposite to the first polarity (e.g., a discharge current). The circuit further comprises a first circuit configured to receive a bias input, a second circuit configured to receive a coarse control input, and a third circuit configured to receive a fine control input. The first circuit is further configured to provide the first current in response to the bias input. The second circuit is further configured to provide the second current in response to the coarse control input, such that the second current generally has a magnitude of from zero to a multiple of the magnitude of the first current.