Abstract: An differential LNA has first and second input MOS transistors, with differential inputs applied to their respective control gates and differential outputs taken at their respective drains. The gate-to-drain, Cgd, feedback capacitances of the first and second input MOS transistors are neutralized by respective gate-to-source, Cgs, capacitances in the two neutralizing MOS transistors. A first neutralizing MOS transistor has its control gate coupled to the control gate of the first input MOS transistor, its source node coupled to the drain node of the second input MOS transistor, and its drain node coupled to a fixed potential. A second neutralizing MOS transistor has its control gate coupled to the control gate of the second input MOS transistor, its source node coupled to the drain node of the first input MOS transistor, and its drain node coupled to the same fixed potential.

Abstract: A method, algorithm, software, architecture, circuit, and/or system for detecting an idle condition and maintaining a frequency of a clock/data recovery circuit are disclosed. In one embodiment, a method of maintaining a frequency of a clock/data recovery circuit can include the steps of: (i) comparing a difference value from a differential signal with a predetermined threshold (or value); (ii) controlling a variable frequency oscillator (VFO) with a frequency detector when the difference value is less than the threshold for at least a predetermined integration time; and (iii) controlling the VFO with a phase detector receiving the differential signal when the difference value is greater than the threshold. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for clock data recovery (CDR) circuits operable with low power mode transmitters.

Abstract: A frequency synthesizer suitable for integration in a low voltage digital CMOS process controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls the center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop, thus eliminating any static frequency error. In effect, the analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made much smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This gross parametric difference is used in the design of the VCO to allow two separate control inputs, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.