Abstract: Thermally sensitive wear leveling for a flash memory device that includes a plurality of flash memory modules, the flash memory device included in a computing system that includes a plurality of additional computing components, including: identifying a thermal sensitivity coefficient for each flash memory module in dependence upon a physical topology of the flash memory device and one or more of the additional computing components; identifying wear leveling information for each flash memory module; receiving a request to write data to the flash memory device; selecting, in dependence upon the thermal sensitivity coefficient for each flash memory module and the wear leveling information for each flash memory module, a target flash memory module for servicing the request to write data to the flash memory device; and writing the data to the target flash memory module.

Abstract: Thermally sensitive wear leveling for a flash memory device that includes a plurality of flash memory modules, the flash memory device included in a computing system that includes a plurality of additional computing components, including: identifying a thermal sensitivity coefficient for each flash memory module in dependence upon a physical topology of the flash memory device and one or more of the additional computing components; identifying wear leveling information for each flash memory module; receiving a request to write data to the flash memory device; selecting, in dependence upon the thermal sensitivity coefficient for each flash memory module and the wear leveling information for each flash memory module, a target flash memory module for servicing the request to write data to the flash memory device; and writing the data to the target flash memory module.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: Detecting TIM between a heat sink and an integrated circuit, the heat sink including TIM detection points, each TIM detection point adapted to receive TIM upon installation of the heat sink, each TIM detection point including a TIM detection device configured to be activated upon contact with TIM, including: receiving, upon installation of the heat sink on the integrated circuit and the TIM, TIM in one or more of the TIM detection points; activating, by the TIM in each of the one or more TIM detection points receiving the TIM, a TIM detection device; and determining, by a TIM detection module in dependence upon the activations of the TIM detection devices, sufficiency of the TIM between the heat sink and the integrated circuit.

Abstract: A system comprises a plurality of fans, wherein each of the fans is configurable to run at a unique fan speed that is different from fan speeds of other fans from the plurality of fans. A plurality of variable-positioned devices, capable of being positioned at various locations within the system, are physically positioned such that airflow from one of the plurality of fans strikes a particular variable-positioned device. A plurality of anemometers, each of which is connected to a particular variable-positioned device, measure airflow across the variable-positioned devices. A system controller, which contains location information that identifies a physical position within the system of each of the plurality of fans, utilizes airflow readings from each of the anemometers to identify a physical location of each of the plurality of variable-positioned devices by matching physical locations of the fans to measured airflow across the variable-positioned devices.

Abstract: Detecting TIM between a heat sink and an integrated circuit, the heat sink including TIM detection points, each TIM detection point adapted to receive TIM upon installation of the heat sink, each TIM detection point including a TIM detection device configured to be activated upon contact with TIM, including: receiving, upon installation of the heat sink on the integrated circuit and the TIM, TIM in one or more of the TIM detection points; activating, by the TIM in each of the one or more TIM detection points receiving the TIM, a TIM detection device; and determining, by a TIM detection module in dependence upon the activations of the TIM detection devices, sufficiency of the TIM between the heat sink and the integrated circuit.

Abstract: Systems and methods for altering movement of mobile communication devices based on determined movements are disclosed. According to an aspect, a method may include determining movement of a mobile communication device. The method may also include determining whether the movement of the mobile communication device meets a predetermined criterion. Further, the method may include controlling a mechanism of the mobile communication device for altering movement of the mobile communication device in response to determining that the movement meets the predetermined criterion.

Abstract: A method of determining power fault information using a voltage regulator-down (VRD) device having a fault-pin output is provided. The method may include receiving a fault indication from one of a plurality of fault detection devices, correlating the received fault indication with a timing signal having a predetermined time duration, applying a voltage change on the fault-pin output of the VRD device for the predetermined time duration corresponding to the timing signal, and applying the voltage change on the fault-pin output to a plurality of fuses. Based on the predetermined time duration associated with the applied voltage change, the plurality of fuses may be blown according to a binary pattern indicative of a fault type associated with the fault indication.

Abstract: In an approach to design and build a capacitor with an integrated indicator of operation above a specified voltage rating, a light emitting device is calibrated to illuminate in response to a level of electrical stimulation and a resistor connected to the light emitting device wherein, the resistance of the resistor is determined at least in part by to the calibration of the light emitting device. The capacitor core with a specified voltage rating for operation has at least a first capacitor lead and a second capacitor lead wherein the first capacitor lead connects to the resistor and the second capacitor lead connects to the light emitting device. A protective coat covers each of the connections between the light emitting device, the resistor, and the capacitor core, such that the light emitting device is visible.

Abstract: A computer determines a characteristic corresponding to each of a first power source and a second power source. The first and second power sources are connected to one or more power distribution units and are configured to provide power in a datacenter. The characteristic includes at least one of a current, a resistance, a voltage, a frequency, a phase, and a magnetic field. The computer generates a comparison of the characteristic corresponding to the first power source and the second power source, to a threshold value of the characteristic. The computer determines if the comparison violates the threshold value of the characteristic. In response to determining the comparison does not violate the threshold value of the characteristic, the computer determines that the first power source and the second power source are connected to a given power distribution unit included in the one or more power distribution units.

Abstract: Increasing data transmission rate in an I2C system that includes an I2C source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: Computing device interface connectors for PCI compliant devices and other devices are disclosed. According to an aspect, an apparatus includes a PCI compliant device residing on a computing device. Further, the apparatus includes another device such as a network controller sideband interface (NCSI) compliant device residing on the computing device. The apparatus also includes an interface connector being communicatively connected to the PCI compliant device and the NCSI compliant device.

Abstract: Computing device interface connectors for PCI compliant devices and other devices are disclosed. According to an aspect, an apparatus includes a PCI compliant device residing on a computing device. Further, the apparatus includes another device such as a network controller sideband interface (NCSI) compliant device residing on the computing device. The apparatus also includes an interface connector being communicatively connected to the PCI compliant device and the NCSI compliant device.

Abstract: A method includes sensing ambient conditions in a datacenter containing a server, and determining whether the ambient conditions exceed predetermined threshold conditions representing risk of electrostatic discharge. A lid to the server is locked in a closed position in response to the ambient conditions exceeding the predetermined threshold conditions. However, the lid to the server is unlocked in response to a grounding strap being connected to the server. Optionally, the grounding strap may be identified and the server lid will only unlock if the identified grounding strap is associated with authorization to unlock the server lid.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: The presence of devices attached to a bus are detected by a controller of a bus transmitting a signal on a channel of the bus, to cause each device to hold the channel to a first logical state for a duration of time that is unique to each device. The device that holds the channel to the first logical state for the longest duration of time is detected. Detected devices remain idle while undetected devices repeat holding the channel to the first logical state for the duration of time, until detected. All devices are detected when the channel returns to a second logical state.

Abstract: A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.