Abstract: Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.

Abstract: Selectively filtering incoming communications events in a communications device, including: receiving, by a communications event filtering module, an incoming communications event; determining, by the communications event filtering module, whether the communications device is currently servicing a call; responsive to determining that the communications device is currently servicing a call, determining, by the communications event filtering module, whether the call is interruptible; and responsive to determining that the call is not interruptible, blocking, by the communications event filtering module, the incoming communications event from presentation by the communications device until the call has ended.

Abstract: Providing noise protection in a signal transmission system that includes a first component, second component, controller, switch, and pre-charged capacitor, the first and second components coupled by a signal line, the controller coupled to the switch, the switch configured to couple the signal line to the capacitor when activated, where providing noise protection includes: determining, by the controller, that a signal transmitted on the signal line transitioned to a steady state voltage; enabling, by the controller responsive to determining that the signal transitioned to the steady state voltage, noise protection to the signal on the signal line including activating the switch thereby coupling the signal line to the pre-charged capacitor, the pre-charged capacitor providing noise protection to the signal on the signal line; and prior to the signal on the signal line transitioning from the steady state voltage, deactivating the switch, thereby decoupling the signal line from the pre-charged capacitor.

Abstract: The presence of devices attached to a bus are detected by a controller of a bus transmitting a signal on a channel of the bus, to cause each device to hold the channel to a first logical state for a duration of time that is unique to each device. The device that holds the channel to the first logical state for the longest duration of time is detected. Detected devices remain idle while undetected devices repeat holding the channel to the first logical state for the duration of time, until detected. All devices are detected when the channel returns to a second logical state.

Abstract: A computer determines a characteristic corresponding to each of a first power source and a second power source. The first and second power sources are connected to one or more power distribution units and are configured to provide power in a datacenter. The characteristic includes at least one of a current, a resistance, a voltage, a frequency, a phase, and a magnetic field. The computer generates a comparison of the characteristic corresponding to the first power source and the second power source, to a threshold value of the characteristic. The computer determines if the comparison violates the threshold value of the characteristic. In response to determining the comparison does not violate the threshold value of the characteristic, the computer determines that the first power source and the second power source are connected to a given power distribution unit included in the one or more power distribution units.

Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.

Abstract: In one embodiment, a memory module connector includes sidewalls extending along a length of the connector body. A longitudinally oriented socket is provided between the sidewalls for receiving a card edge of a memory module. A top of the connector defines a socket opening. A bottom of the connector is for mounting to a system board. A plurality of air deflectors is provided adjacent to the connector body to manipulate airflow to improve cooling. The size, positioning, and spacing of the air deflectors may be selected to optimize cooling.

Abstract: A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.

Abstract: Providing noise protection in a signal transmission system that includes a first component, second component, controller, switch, and pre-charged capacitor, the first and second components coupled by a signal line, the controller coupled to the switch, the switch configured to couple the signal line to the capacitor when activated, where providing noise protection includes: determining, by the controller, that a signal transmitted on the signal line transitioned to a steady state voltage; enabling, by the controller responsive to determining that the signal transitioned to the steady state voltage, noise protection to the signal on the signal line including activating the switch thereby coupling the signal line to the pre-charged capacitor, the pre-charged capacitor providing noise protection to the signal on the signal line; and prior to the signal on the signal line transitioning from the steady state voltage, deactivating the switch, thereby decoupling the signal line from the pre-charged capacitor.

Abstract: A method uses scales onboard a lift apparatus to weigh an uninstalled component that is positioned on the lift apparatus for installation into a rack. Data is accessed that identifies the weight and rack location of components currently installed in the rack, and one or more available rack locations are identified where the component may be installed without violating one or more predetermined rack stability rules. The method then uses the lift apparatus to raise the component into a selected one of the one or more available rack locations. The components are preferably information technology components, such as servers, network switches and power distribution units.

Abstract: Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

Abstract: In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.

Abstract: A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device.

Abstract: Increasing data transmission rate in an I2C system that includes an I2C source device and an destination device, the source device coupled to the destination device through an SDL and SCL, including: receiving in parallel, by the destination device, an SDL data signal and an SCL data signal, the SCL data signal encoded with bits; and, for each bit of the SCL data signal: detecting rise time of the bit and determining, in dependence upon the detected rise time, whether the bit represents a first binary value or a second binary value including: determining that the bit represents a first binary value when the detected rise time is less than a predefined threshold; and determining that the bit represents a second binary value when the detected rise time is not less than the predefined threshold.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.

Abstract: A heat sink comprises a base and a fin support larger in area than the base and supporting fins that may be positioned in a plurality of orientations relative to the base. The base is adapted for being connected to a heat-generating electronic component on a circuit board, and the heat sink dissipates heat generated by the heat-generating electronic device and conducted through the base and the fin support to the fins supported thereon. The heat sink dissipates heat from the heat-generating electronic device in a first operable position and in a second operable position. The heat sink may be moved from the first to the second operable position to facilitate access to electrical contacts proximal the heat-generating electronic component.

Abstract: Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.

Abstract: A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.

Abstract: An electronic component is connected to a circuit board by forming a connector pin on the electronic component, the connector pin having a proximate end secured to the electronic component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through-hole is formed on a circuit board having a circuit board thickness greater than a length of the connector pin, with a first portion that is narrower than each of the compliant portion and the fork lock and extends partially through the circuit board and a second portion that extends beyond the first portion and is wider than the first portion. The connector pin is inserted into the first portion of the through-hole and the fork lock is moved beyond the first portion into the second portion of the through-hole.