Abstract: A method for compressing an integrated circuit model has steps of selecting a first net and compressing at least a second net connected to the first net by removing resistors and summing capacitors. Through steps of the present invention, the size and complexity of the integrated circuit model are thereby simplified while retaining information regarding the second net that may be required for analysis.

Abstract: A method for identifying FETs implemented in a predefined logic equation defined by at least one signal name from a netlist having output nodes, supply voltages with their opposite supply voltages, and FETs with their connectivity, that includes the steps of selecting an output node from the netlist, preparing the predefined logic equation for searching FETs in the netlist, and identifying FETs from the netlist that are implemented in the prepared predefined logic equation.

Abstract: A method for generating a configuration database file based on at least one data file of at least one ECAD tool included in a predefined tool list, which includes the steps of selecting an ECAD tool from the predefined tool list, reading a data file of the selected ECAD tool and generating a configuration database file based on the read data file.

Abstract: A method for identifying dynamic NAND or NOR gates from a netlist having output nodes, supply voltages along with their opposite supply voltages, FETs and their connections, which includes the steps of selecting an output node from the netlist, identifying FETs having at least one branch that is connected directly to the selected output node but not connected directly to the supply voltage, verifying that the branch(es) of the identified FETs define a dynamic logic gate, and identifying either a NAND gate or a NOR gate for the dynamic logic gate.

Abstract: A method is disclosed for storing a circuit design in memory of a computer system and analyzing the design using an electronic computer-aided design (E-CAD) tool. The design may include hierarchical cells for repeated elements and groups of elements. A flat data structure is created to represent a specified portion of the circuit between two terminal nodes. For each node and edge in the specified portion, the flat data structure stores a name, an address pointer to the underlying data in the circuit model, and address pointers to adjoining nodes or edges in the flat data structure. Also for each node and edge in the design, the data structure stores an indicator showing whether the node or edge has been analyzed. The E-CAD analysis is performed on the flat representation, the results are recorded, and the flat data structure is deleted from memory.

Abstract: A method is disclosed for storing a circuit design in memory of a computer system and analyzing the design using an electronic computer-aided design (E-CAD) tool. The design may include hierarchical cells for repeated elements and groups of elements. A flat data structure is created to represent a specified portion of the circuit between two terminal nodes. For each node and edge in the specified portion, the flat data structure stores a name, an address pointer to the underlying data in the circuit model, and address pointers to adjoining nodes or edges in the flat data structure. Also for each node and edge in the design, the data structure stores an indicator showing whether the node or edge has been analyzed. The E-CAD analysis is performed on the flat representation, the results are recorded, and the flat data structure is deleted from memory.

Abstract: A configuration software tool is disclosed for analyzing circuit design violations detected by an E-CAD tool and proposing solutions. An E-CAD tool analyzes a circuit design and outputs violations of design specifications. The configuration tool reads the violations to identify symptoms. The configuration tool accesses a solutions database that stores solutions to common violations encountered with the design. Based on the symptoms, the configuration tool outputs possible solutions for each violation. The user selects one of the proposed solutions or another solution. Based on the selected solution, the configuration tool edits the configuration file of the E-CAD tool. Once all solutions are resolved, the E-CAD tool is re-run on the design. The configuration tool may be stored in a computer system that operates the E-CAD tool, or it may be stored in a remote location accessed by multiple computer systems, such as network server connected to the computer systems.

Abstract: A method is disclosed for analyzing a VLSI circuit design stored in a computer system. Each segment of the design layout is stored in the computer memory for analysis and implementation. An electronic computer-aided design (E-CAD) program is used to analyze the design. First, the E-CAD tool is run on the entire design or on a designated part thereof. The tool compares the design to specifications and returns a list of violations on a segment basis. The E-CAD tool identifies violations for the designer to fix through redesign or clarification of specifications. The method marks or flags signals of those segments reporting violations. After the designer has attempted to remedy the violations, the method reruns the E-CAD analysis on those signals that reported a violation during a prior run.

Abstract: A method is disclosed for identifying FETs that comprise NAND and NOR logic gates in a circuit design having numerous FETs. A potential logic gate output node is queried to determine the configuration of FETs around the output node. FETs connected directly between the output node and either a high or low potential (VDD or GND) are identified and stored to memory along with a their corresponding gate signals. Branch FETs that are of a different type than the directly-connected FETs and that are channel-connected between the output node and either VDD or GND are also identified. If a gate signal for each FET in a branch corresponds to a gate signal of a directly-connected FET at the same output node, then a logic gate exists.