Abstract: A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture.

Abstract: The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.

Abstract: The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.

Abstract: The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET). Some embodiments may include a power MOSFET with transistor cells, each cell comprising a source and a drain region; a first dielectric layer disposed atop the transistor cells; a silicon rich oxide layer on the first dielectric layer; grooves through the multi-layered dielectric, each groove above a respective source or drain region and filled with a conductive material; a second dielectric layer atop the multi-layered dielectric; openings in the second dielectric layer, each opening exposing a contact area of one of the plurality of grooves; and a metal layer disposed atop the second dielectric layer and filling the openings. The metal layer may form at least one drain metal wire and at least one source metal wire. The at least one drain metal wire may connect two drain regions through respective grooves.

Abstract: The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET) and methods for their manufacture.

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Abstract: A semiconductor power chip may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; a plurality of ball bumps or a loaf bump disposed on each of the plurality of second elements and the plurality of third elements; and at least one ball bump or loaf on the at least one first contact element.

Abstract: High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract: A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract: At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die.

Abstract: High voltage rated isolation capacitors are formed on a face of a primary integrated circuit die. The isolation capacitors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors, and a larger value capacitor in the second voltage domain may provide for peak current demand from circuits in the second voltage domain.

Abstract: An improved field effect transistor (FET) is provided by segmenting the gates of a power FET wherein a controller can “decide” how much of the FET to use, thus increasing efficiency.

Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.

Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.