Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A method for manufacturing a Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has the step of implanting a base region of said MOSFET within an epitaxial layer of a semiconductor chip comprising an insulated gate structure used as a masking element, wherein the implant beam is angled with respect to a vertical axis of the semiconductor chip such that the base region extends sufficiently under the gate to form a Power-MOSFET.

Abstract: A semiconductor power chip may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; a plurality of ball bumps or a loaf bump disposed on each of the plurality of second elements and the plurality of third elements; and at least one ball bump or loaf on the at least one first contact element.

Abstract: A method for manufacturing a Power Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has the steps of: implanting a base region of the Power MOSFET within an epitaxial layer of a semiconductor chip comprising an insulated gate structure, implanting a source link region on one side of the gate through a first mask, wherein the first mask is partially formed by an edge of the gate, the source link extending from a surface into the epitaxial layer and having a width defined by the first window, subsequently forming a spacer extending from the edge of the gate which defines the first window and forming a second mask which is partially formed by the spacer, and implanting a source region through the second mask.

Abstract: A method for producing a power field effect transistor (FET) device having a low series resistance between the drain and source when switched on has the steps of: forming a vertical power FET in a semiconductor die; and back-grinding the semiconductor die to a thickness of less than or equal to about 100 ?m (4 mils) or less.

Abstract: A method for forming an epitaxial layer on a substrate may have the steps of: forming a heavily doped silicon substrate; depositing an epitaxial layer at sub atmospheric pressure on the heavily doped silicon substrate; and implanting dopant into the epitaxial layer by ion implantation to form a lightly doped epitaxial layer.

Abstract: A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET), has a cell structure with a substrate; an epitaxial layer or well of the first conductivity type on the substrate; first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged within the first and second base region, respectively; a gate structure insulated from the epitaxial layer or well by an insulation layer and arranged above the region between the first and second base regions and covering at least partly the first and second base region, wherein the gate structure comprises first and second gates being spaced apart wherein each gate covers a respective portion of the base region.

Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A temperature compensated voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. The transistor widths of two P-MOS transistors are adjusted to minimize voltage variation over a temperature range.

Abstract: A voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference.

Abstract: A temperature compensated voltage reference is created from an operational amplifier circuit having two substantially identical P-channel metal oxide semiconductor (P-MOS) transistors with each one having a different gate dopant. The different gate dopants result in different threshold voltages for each of the two otherwise substantially identical P-MOS transistors. The difference between these two threshold voltages is then used to create the voltage reference equal to the difference. The two P-MOS transistors are configured as a differential pair in the operational amplifier circuit and the output of the operational amplifier is used as the voltage reference. The transistor widths of two P-MOS transistors are adjusted to minimize voltage variation over a temperature range.