Abstract: Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

Abstract: Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a plurality of data bits each corresponding to a binary indication of a test result; placing each of the plurality of data bits on an approximation circuit, wherein each of the data bits is placed on the approximation circuit by applying, to a first capacitor during a set time period, a voltage corresponding to the data bit, and wherein placing each of the plurality of data bits on the approximation circuit results in a resulting voltage stored on the first capacitor; and determining a potential correlation of the test results by comparing the resulting voltage to a voltage threshold.

Abstract: Cognitive analysis using applied analog circuits including receiving, by a circuit, a first set of data results and a second set of data results; charging a first capacitor on the circuit with a first unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with a second unit of charge for each of the second set of data results that indicates a positive data point; applying a charge from the first capacitor and a charge from the second capacitor to an analog unit of the circuit; and generating a signal on a circuit output indicating that a ratio of the positive data points in the first set of data results to the positive data points in the second set of data results is greater than a statistical significance.

Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.

Abstract: Real time cognitive monitoring of correlations between variables including receiving, by a circuit, a first set of data results and a second set of data results, wherein each set of data results comprises binary data points; adding a unit of charge to a collection capacitor on the circuit for each of the first set of data results that indicates a positive data point; removing a unit of charge from the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the circuit if the charge on the collection capacitor exceeds a high charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance.

Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.

Abstract: Real time cognitive monitoring of correlations between variables including receiving, by a circuit, a first set of data results and a second set of data results, wherein each set of data results comprises binary data points; adding a unit of charge to a collection capacitor on the circuit for each of the first set of data results that indicates a positive data point; removing a unit of charge from the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the circuit if the charge on the collection capacitor exceeds a high charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance.

Abstract: Cognitive analysis using applied analog circuits including receiving, by a circuit, a first set of data results and a second set of data results; charging a first capacitor on the circuit with a first unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with a second unit of charge for each of the second set of data results that indicates a positive data point; applying a charge from the first capacitor and a charge from the second capacitor to an analog unit of the circuit; and generating a signal on a circuit output indicating that a ratio of the positive data points in the first set of data results to the positive data points in the second set of data results is greater than a statistical significance.

Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.

Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.

Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

Abstract: Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.

Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.

Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)* a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

Abstract: Big data analysis using low power circuit design including storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline; precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit; activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells; and measuring a resulting voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: Generating a unique die identifier for an electronic chip including placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, wherein each of the set of test circuits is attached to a corresponding component on the electronic chip; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits: selecting the race pair of test circuits; executing a race between the selected race pair; and adding an element to the unique die identifier based on an outcome of the executed race; and returning the electronic chip to an operational state.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.