Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

Abstract: A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single FET. The fin also may have a top fin area that is wider than the body area and is electrically independent from the two FETs. The top fin area may be capable of receiving a body contact structure which may be connected to an electrical conductor as to regulate the voltage in the body area of the fin.

Abstract: A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin.

Abstract: A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: A method for fabricating a resistor in a dielectric layer of an integrated circuit (IC) is disclosed. The method may include creating a trench with a first side, a second side opposing the first side, and a bottom, in the dielectric layer, and depositing a conformal film onto the first side, the second side and the bottom of the trench. The method may also include removing the conformal film from the bottom and the second side of the trench, and filling the trench with an insulator. The method may also include removing the conformal film from the first side of the trench to form a receptacle adjacent to the insulator, and depositing electrically resistive material into the receptacle to form a resistor.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: Methods and structures implement enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas for contacting one or more metal wiring layers on a semiconductor chip. A first wiring level in the TSV exclusion zone area includes a first wiring shape having a first hole of a first diameter. A dielectric includes second hole of a second diameter larger than the first diameter is provided above the first wiring level concentric with the first hole. A via hole extends through the first and second holes and an etch is performed to expose a top surface portion of the first wiring shape. A thin oxide is grown over the entire bore of the hole; an anisotropic etch is provided to remove horizontal portions of the thin oxide, exposing wiring shapes. The via hole is filled with a selected material to make TSV electrical connection to the exposed wiring shape.

Abstract: An apparatus includes a first radiation detector to generate a first signal when a first radiation level is exceeded and a second radiation detector to generate a second signal when a second radiation level is exceeded. The second radiation level is greater than the first radiation level. A first circuit is susceptible to soft errors at the first radiation level and a second circuit is susceptible to soft errors at the second radiation level. A control unit may suspend use of the first circuit and activate use of the second circuit if the first signal is received and the second signal is not received. The first and second circuits may be memory cells or logic circuits.

Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

Abstract: Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.

Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

Abstract: A finFET includes a semiconductor fin formed on a base. The fin further includes a body area between a first vertical surface and a second vertical surface. The finFET includes a first contact adjacent to the first vertical surface of the body area. The first vertical surface is spaced away from the first contact by a first dielectric thickness. Also included is a second contact adjacent to the second vertical surface of the body area. The second vertical surface is spaced away from the second contact by a second dielectric thickness. The first dielectric thickness and second dielectric thickness are configured to allow the first contact and second contact to modulate the body area of the fin.

Abstract: A semiconductor chip includes a semiconductor on insulator structure having a frontside and a backside. The chip includes a circuit in the semiconductor layer at the frontside. The circuit is isolated from a substrate. The chip includes a through silicon via (TSV) having a front-end, a back-end, and a lateral surface. The TSV is in the semiconductor layer and buried oxide layer and the front-end surface of the TSV is substantially parallel to the frontside of the semiconductor layer. An antifuse is deposited between the back-end of the TSV and the substrate. The antifuse insulates the TSV from the substrate. A ground layer is insulated from the semiconductor on insulator structure, and is coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion the antifuse to migrate away from the TSV, thereby connecting the circuit to the ground.

Abstract: Methods and structures implement enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas for contacting one or more metal wiring layers on a semiconductor chip. A first wiring level in the TSV exclusion zone area includes a first wiring shape having a first hole of a first diameter. A dielectric includes second hole of a second diameter larger than the first diameter is provided above the first wiring level concentric with the first hole. A via hole extends through the first and second holes and an etch is performed to expose a top surface portion of the first wiring shape. A thin oxide is grown over the entire bore of the hole; an anisotropic etch is provided to remove horizontal portions of the thin oxide, exposing wiring shapes. The via hole is filled with a selected material to make TSV electrical connection to the exposed wiring shape.

Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

Abstract: A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip.

Abstract: A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.

Abstract: A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin.