Patents by Inventor Gregory L. DeJager
Gregory L. DeJager has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7480309Abstract: The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.Type: GrantFiled: March 7, 2005Date of Patent: January 20, 2009Assignee: Cisco Technology, Inc.Inventors: Gregory L. DeJager, James R. Rivers, David H. Yen, Stewart Findlater, Scott A. Emery
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Patent number: 6934293Abstract: The network switches and computer readable mediums of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.Type: GrantFiled: October 10, 2003Date of Patent: August 23, 2005Assignee: Cisco Technology, Inc.Inventors: Gregory L. DeJager, James R. Rivers, David H. Yen, Stewart Findlater, Scott A. Emery
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Patent number: 6667975Abstract: Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.Type: GrantFiled: September 19, 2002Date of Patent: December 23, 2003Assignee: Cisco Technology, Inc.Inventors: Gregory L. DeJager, James R. Rivers, David H. Yen, Stewart Findlater, Scott A. Emery
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Patent number: 6473424Abstract: Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.Type: GrantFiled: December 2, 1998Date of Patent: October 29, 2002Assignee: Cisco Technology, Inc.Inventors: Gregory L. DeJager, James R. Rivers, David H. Yen, Stewart Findlater, Scott A. Emery
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Patent number: 6078532Abstract: A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.Type: GrantFiled: February 1, 1999Date of Patent: June 20, 2000Assignee: Cisco Technology Inc.Inventors: James P. Rivers, Gregory L. DeJager, David H. Yen, Stewart Findlater, Bradley Erickson, Scott A. Emery
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Patent number: 5875210Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as a repeater in a communication system. The PHY repeater supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. When the pass all symbols, pass violation symbols and pass line states modes are enabled, the PHY device operates as a "transparent" repeater. The repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The repeater also allows line states to be repeated without station management software. A single repeater may be used to couple two stations or multiple repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.Type: GrantFiled: February 13, 1997Date of Patent: February 23, 1999Assignee: National Semiconductor CorporationInventors: David C. Brief, Gregory L. DeJager, James R. Hamstra
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Patent number: 5784404Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.Type: GrantFiled: January 19, 1996Date of Patent: July 21, 1998Assignee: National Semiconductor CorporationInventors: David C. Brief, Gregory L. DeJager, James R. Hamstra
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Patent number: 5566203Abstract: A physical layer (PHY) device which can operate as a conventional PHY or as an intelligent repeater in a communication system. The PHY device supports four optional modes which may be enabled by programming control register bits with a microcontroller. These optional modes are: pass all symbols, enable noise filter, pass violation symbols and pass line states. During operation as an intelligent repeater, the pass all symbols, pass violation symbols and pass line states modes are enabled. The intelligent repeater allows errors in a data stream to be encoded and repeated without filtering to a downstream station. The intelligent repeater also allows line states to be repeated without station management software. A single intelligent repeater may be used to couple two stations or multiple intelligent repeaters may be connected to form multi-port repeater boxes which can be connected to facilitate more reliable connections between stations.Type: GrantFiled: June 24, 1993Date of Patent: October 15, 1996Assignee: National Semiconductor Corp.Inventors: David C. Brief, Gregory L. DeJager, James R. Hamstra
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Patent number: 5533018Abstract: An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory.Type: GrantFiled: December 21, 1994Date of Patent: July 2, 1996Assignee: National Semiconductor CorporationInventors: Gregory L. DeJager, Erik R. Swenson
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Patent number: RE38820Abstract: An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to cause incoming data to be deframed by the appropriate framer/deframer circuit depending on which slot of the network frame contained the information. Once deframed, a buffer manager controls storing of the information in a circular ring buffer in an external memory.Type: GrantFiled: July 2, 1998Date of Patent: October 11, 2005Assignee: Negotiated Data Solutions LLCInventors: Gregory L. Dejager, Erik R. Swenson